Abstract
This paper presents a novel PWAM signaling scheme, which combines a dual-mode pulse amplitude modulation-4 (dual-mode PAM-4) and a pulse width modulation-2 (PWM-2). Its combination is different from that of the conventional PWAM scheme [4]. So, the minimum pulse width of the proposed PWAM scheme is increased. The proposed PWAM scheme can reduce the power consumption of the transceiver by decreasing the number of differential levels (X) compared with the existing 4-bit/symbol PAM-X scheme (i.e., dual-mode PAM-10 [2] and PAM-16 [13]). The proposed PWAM transceiver was designed in a 180 nm CMOS process, and it has a target of 10-Gb/s. The power consumption of the transmitter and receiver is 134 ㎽ and 95 ㎽, respectively. The power efficiency of the transmitter and receiver are 13.4 pJ/bit and 9.5 pJ/bit, respectively.
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