Abstract
This paper describes a packet-based overhead-reduced (OR) key coding technique for a high-speed serial interface. The 8B10B code is a de facto standard coding technique in the application but its bit-overhead is 25%. The proposed key coding technique is to reduce the coding overhead and still provides enough bit transition to facilitate clock and data recovery in the receiver. After a key pattern is generated from a certain data stream, input data are encoded and framed as packets along with the generated key for transmission. The packets are transmitted and then decoded as original data in the receiver. Using the proposed coding scheme, 4-, 6-, and 8-bit key coding systems are designed and compared. When a 6-bit key coding encoder/decoder is tested, a packet is composed of a 6-bit OR key header followed by 30 encoded sub-packets, in which each sub-packet has a 6-bit data. In the 6-bit case, the bit overhead is only 3.33% and the maximum continuous run length is 10 bits. To control the running disparity for the AC coupling interface, a logic for selecting the optimal key is implemented to keep the running disparity as low as possible. The running disparity of the encoded data with 6-bit key code is controlled within +/−12.
Highlights
As technology advances, higher data rate transmission is required in optical communications, digital video, memory, data storage systems, and other high-speed serial interfaces
Its running disparity is controlled within +/-2; it is suitable as an AC coupling interface
64B66B code is being used in optical communication systems [3] and it has the bit-overhead of 3.12%, but the maximum run length is 66 bits, which requires a tighter clock and data recovery (CDR) circuit design
Summary
Higher data rate transmission is required in optical communications, digital video, memory, data storage systems, and other high-speed serial interfaces. 64B66B code is being used in optical communication systems [3] and it has the bit-overhead of 3.12%, but the maximum run length is 66 bits, which requires a tighter clock and data recovery (CDR) circuit design. Work was done on a 24B27B code with DC balancing for display interface [6] This scheme reduces the overhead to 12.5% with running length to 8 bits and adds a block to control the running disparity. As PAM-4 signaling has gotten attention in high-speed interface applications, DC-balancing PAM-4 coding techniques have been published [7, 8] Their overhead ratio stayed the same as that of 8B10B, which is 25%. Bak et al.: An Overhead-Reduced Coding Technique for High-Speed Serial Interface
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