A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces

Abstract

We report on the development of a time-domain numerical modeling framework to estimate timing jitter in High-Speed Serial Interfaces (HSSI) including a wide range of effects such as Inter-Symbol Interference (ISI) due to channel dispersion, phase noise of transmitter (TX) and receiver (RX) frequency synthesizers and use of bang-bang phase detector in the Clock and Data Recovery (CDR) loop. Based on the step response of the channel, the numerical model computes the response of the system to a random sequence of bits and provides information in terms of eye diagram, bathtub plot and jitter histogram. Different definitions of jitter are investigated, and for each of them we consider the physical effects that are included, eventually identifying that the most complete definition is based on the time distance between the edges instants defined by the CDR and the crossing points of the sampled signal. We also found that this definition is consistent with the features of the bathtub plot. A channel compliant with the PCIe 4.0 standard is used as test vehicle, including the main equalization strategies. The numerical model is then compared to a simple analytical model for the CDR jitter that can be augmented by including Data-Dependent Jitter (DDJ). An approach to system-level analysis based on proper combination of the above elements is eventually proposed to provide quick although accurate aid to the design of CDRs in HSSIs.