High-speed Serial Interface Research Articles

A scalable voltage controlled oscillator for multi-rate high-speed interfaces

This paper proposes a voltage controlled oscillator (VCO) which is based on a pseudo-differential ring oscillator suitable for multi-Gbps serial interfaces. The delay element employed in the ring oscillator topology consists of two CMOS inverters loaded by a simple negative resistance realized with pMOS transistors. The proposed topology is designed and simulated in a 65nm CMOS process with 1.2V supply voltage. As a realistic application, the VCO performance is optimized to be compliant with the MIPI Alliance M-PHY standard which is the most updated high-speed serial interface technology. The frequency tuning range covers the three frequency bands of the MPHY standard which are [0.624 and 0.7288]GHz, [1.248 and 1.4576]GHz and [2.496 and 2.9152]GHz and corresponds to high-speed gear 1,2 and 3, respectively. In each gear an almost constant KVCO is achieved while the current consumption of the whole system is 2.87, 5.19 and 10.06mA for the gears 1,2 and 3, respectively. The phase noise is about −94dBc/Hz at 1MHz frequency offset for 2.9152GHz.

Design of a High-Speed Serial Programming Interface Compatible with Bluetooth Embedded Systems

In this paper, we designed a serial programming interface (SPI) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. The 8-bit design of the SPI module is in charge of transferring the data and the instructions between the external devices and the coprocessors. We adopted the cyclic redundancy check method for the error correction. Also, we provided the interface for multimedia cards. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.

An Adaptive Equalizer for High-Speed Receiver using a CDR-Assisted All-Digital Jitter Measurement

An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20”, 30”, 40” FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a 0.13 μm process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.

SFP + High-Speed Channel Performance Simulation and Measure

The 10Gbps high-speed serial interface has been used in data transmission widely. As the bandwidth demanding for high-speed communication network sharply increases, it is increasingly important to investigate the interconnection of high-speed serial interface. In this paper, the SFP+ interface signal integrity (SI) were analyzed with EM simulation and the lab measurement. The 2.5D and 3D modeling methodologies were introduced for the interest transmission line in the frequency domain. We measured its differential mode (DM) reflection and transmission coefficients, subsequently observed the variation of DM impedance and analyzed the causes of impedance discontinuity by the utilization of TDR measurement, and finally put forward several methods to improve the SI. It is notable that the simulation results of the 2.5D and 3D model are almost identical by comparison, which means that 2.5D modeling methodologies also can achieve high accuracy around 10Ghz. Additionally, we optimized the SI simulation results by varying the output voltage and pre-emphasis parameters. Finally, the SFP+ compliance test shows the simulation has good agreement with lab measurement in the time domain.

Multiscale matched filter-based lane detection scheme of the constant false alarm rate for driver assistance

Real-time lane detection is an important element for driver assistance systems in rapidly changing traffic scenarios. In this paper, an embedded lane detection platform combining a high-dynamic-range image sensor is proposed. As for the software development, a multiscale matched filter scheme is successfully used to enhance the local contrast between the lane markings and the background interference for different traffic scenarios. Then, an intelligent constant-false-alarm-rate detector is designed to generate an adaptive threshold for extraction of the lane markings. As for hardware implementation, a field programmable gate array is used for obtaining a high-dynamic-range image, and then matched filters achieve their optimal design based on the coefficient decomposition technology in the form of a fixed point number. Subsequently, through a high-speed serial peripheral interface bus, all pre-processed data are transferred to an ARM processor, which takes charge of extraction of the lane markings and also lane fitting. Experiments and evaluation prove that the proposed system can effectively detect the lane markings for different traffic scenarios in a time of 11.64 ms for each frame.

UHD급 영상패턴 제어 신호발생기를 위한 고속 시리얼 인터페이스의 신호 무결성 분석

UHD급 영상패턴 제어 신호발생기를 위한 고속 시리얼 인터페이스의 신호 무결성 분석

A Regulator Design for a SerDes PHY of a High Speed Serial Data Interface

A fully integrated 3.3 V-to-1.2 V supply voltage regulator for application in IEEE 1394B PHY has been designed in 0.13μm SMIC Mixed Signal process technology. The regulator is able to deliver peak current transient of 300 mA, while the output voltage remain within a margin of 10% around the nominal value. The PSRR response larger than 52 dB for frequencies up to 10 kHz under the condition of IL=300 mA. The FOM of the circuit can be better than 2.5. The circuit can be used in all types of high speed serial data communication system. Index Terms—On-chip voltage regulator, IEEE 1934B PHY, class-AB.

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

High speed serial interfaces (HSSI) are continually pushed toward operating at higher speed to meet the demand for higher bandwidth. As a result, the timing constraints for HSSI devices get tighter. Consequently, HSSI devices experience issues such as timing jitter and bit-errors. This paper investigates techniques to speed up HSSI bit-error rate and jitter testing. The proposed oversampling-based transmitter test scheme accelerates transmitter jitter and eye diagram testing by means of a multi-phase bit-error rate test circuit (BERT). The proposed scheme creates parallel BERT elements working in conjunction that are able to digitize the input signal jitter behavior in a multi-phase manner. The more phases we deploy the faster the test is completed. We accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds, exceeding the current norm of 100 ms.

A Novel High Speed Serial Interface in UTMI+ Transceivers for USB 2.0 Hub Repeater Operations: A Proposal

A Novel High Speed Serial Interface in UTMI+ Transceivers for USB 2.0 Hub Repeater Operations: A Proposal

A High-Speed Wireless Transmission Scheme for Wireless Sensor Network

Along with more extensive application of wireless sensor network (WSN) technology, real-time and a large amount of data transmission requires WSN system to achieve high-speed transmission. Therefore, a high-speed wireless data transmission scheme is an essential requirement in WSN environment. We propose a modified WiFi (Wireless Fidelity) protocol for wireless transmission and high speed serial peripheral interface, and design a single-node system to test the scheme. The experimental result shows that the average transmission rate of the system can reach 893.1kb/s, meet the demand for high-speed wireless transmission.

A 1.7 Gbps DLL-Based Clock Data Recovery for a Serial Display Interface in 0.35-μm CMOS

This paper presents a delay-locked-loop–based clock and data recovery (CDR) circuit design with a nB(n+2)B data formatting scheme for a high-speed serial display interface. The nB(n+2)B data is formatted by inserting a ‘01’ clock information pattern in every piece of N-bit data. The proposed CDR recovers clock and data in 1:10 demultiplexed form without an external reference clock. To validate the feasibility of the scheme, a 1.7-Gbps CDR based on the proposed scheme is designed, simulated, and fabricated. Input data patterns were formatted as 10B12B for a high-performance display interface. The proposed CDR consumes approximately 8 mA under a 3.3-V power supply using a 0.35-μm CMOS process and the measured peak-to-peak jitter of the recovered clock is 44 ps.

A low power CMOS 3.3 Gbps continuous-time adaptive equalizer for serial link

This paper describes using a high-speed continuous-time analog adaptive equalizer as the front-end of a receiver for a high-speed serial interface, which is compliant with many serial communication specifications such as USB2.0, PCI-E2.0 and Rapid IO. The low and high frequency loops are merged to decrease the effect of delay between the two paths, in addition, the infinite input impedance facilitates the cascade stages in order to improve the high frequency boosting gain. The implemented circuit architecture could facilitate the wide frequency range from 1 to 3.3 Gbps with different length FR4-PCB traces, which brings as much as 25 dB loss. The replica control circuits are injected to provide a convenient way to regulate common-mode voltage for full differential operation. In addition, AC coupling is adopted to suppress the common input from the forward stage. A prototype chip was fabricated in 0.18-μm 1P6M mixed-signal CMOS technology. The actual area is 0.6 × 0.57 mm2 and the analog equalizer operates up to 3.3 Gbps over FR4-PCB trace with 25 dB loss. The overall power dissipation is approximately 23.4 mW.

고속 직렬 디스플레이 인터페이스를 위한 1/4-rate 클록 데이터 복원회로 설계

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard 0.18㎛ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation

Qualifying Serial Interface Jitter Rapidly and Cost-effectively

High-Speed Serial Interface (HSSI) devices have witnessed an increased use in communications. As a measure of how often bit errors happen in a communication interface, Bit Error Rate (BER) performance is of paramount importance. The bit errors in HSSIs are in large part due to jitter. This paper investigates the topic of accelerating the jitter and BER testing. We first present an under-sampling based transmitter test scheme. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100 ms while the test usually takes seconds. Then we propose a jitter tolerance extrapolation algorithm that enables us to perform the receiver jitter tolerance characterization and production test more than 1,000 times faster. The transmitter and receiver testing schemes have been successfully used on Automatic Test Equipment (ATE) to qualify millions of HSSIs with data rates up to 6 Gigabits per second (Gbps). The paper also presents a low cost external loopback-based testing scheme, where a novel jitter injection technique is proposed using the state-of-the-art phase delay line. With the novel jitter injection scheme and an FPGA-based Bit Error Rate Tester (BERT), we can validate and test HSSIs with higher data rates, but without the need of high-speed ATE instruments. Using high-speed relays, we can also utilize ATE to provide a more versatile scheme for HSSI validation, characterization and testing.

The Design of Serial ATA Bus Control Chip

In a PC system, External storage interface is still a bottleneck in spite of its continuous improving performance, in contrast to the fast development of CPU, memory, graphic chips. The transfer rate in ATA protocol has been improved drastically from the beginning 3.3MB/s to current 133MB/s, but the plate electrode of a parallel interface is inevitably puzzled by clock skew, which limit the increasing of frequency and transfer rate can not be improved. Serial ATA protocol is compatible with Parallel ATA protocol in software layer. Its transfer rate is improved greatly due to serial interface with embedded clock. This paper will discuss the differences between Parallel ATA protocol and serial ATA protocol, and describe the hierarchical classification of serial ATA protocol model. Last a design for HPT183, a parallel/serial ATA bridge connection chip will be put forward. In high speed serial interface integrated circuit design, the design of high speed serial data recovery circuit is a troublesome task. In this paper an all-digital high speed serial data recovery circuit module for 1.5bps SATA interface implement is introduced. In contract to other design made from analog circuit, this all-digital circuit is an easily implement design and it has lower power consumption and smaller area. This circuit is being implemented in HPT183 chip which is designed and manufactured using a 0.18um CMOS process. At the end the test performance index for this chip is also provided.

SMIA CCP2 직렬 인터페이스를 가지는 고기능 이미지 센서를 위한 데이터 프로토콜 변환 시스템의 구현

LVDS에 기반을 둔 초고속 저전력 직렬 인터페이스인 SMIA(Standard Mobile Imaging Architecture) CCP2(Compact Camera Port 2) 규격을 채택한 CMOS 이미지 센서들이 개발되면서, 기존의 CMOS 이미지 센서들과 직접 연결되었던 장비들이 사용할 수 없게 되고 있다 본 논문에서는 SMIA CCP2 규격의 직렬데이터 신호를 범용 10-비트 병렬 신호로 변환하는 시스템을 제안하고. 이의 구현 방안을 제시한다. 제안한 데이터 프로토콜 변환 시스템은 de-serializer 1개와 저가의 FPGA로 구성되어 소형 PCB로 구현되어, 장비와 이미지 센서 사이를 추가 공간 없이 용이하게 접속할 수 있다. 또한 SMIA CCP2 규격에서 제시된 최대 속도인 650Mbps의 속도로 데이터를 변환하는 것이 가능하기 때문에 범용 프로토콜 변환 시스템으로서의 활용성도 매우 높을 것으로 기대된다. Recently the high-end CMOS image sensors are developed, conforming to the SMIA CCP2 specification, which is a high-speed low-power serial interface based on LVDS technology. But this kind of technology trend makes the existing equipments are no longer useful, although their capability is still good enough to handle the recent image sensors if there was no interfacing problem. In this paper, we propose and realize a data protocol conversion system that translates the SMIA CCP2 serial signals into the existing 10-bit parallel signals. The proposed system is composed of a de-serializer and a FPCA chip, and thus can be constructed on a small PCB which enables easy integration between the existing equipments and the new high-end image sensors. Besides, the maximum transfer rate by the SMIA specification is also achieved on the implemented system. So it is expected that the implemented system can be used as a general-purpose protocol converter in a variety of sensor-related application fields.

An Embedded System for Position and Speed Measurement Adopting Incremental Encoders

This paper presents an embedded digital system for incremental encoders allowing for high dynamic performance and accuracy speed measurement in all the operating conditions for the application in digital servo drives. The idea aims at embedding processing capabilities inside traditional position transducers in order to develop a smart measuring system. The base processing algorithm employs a novel mixed time and frequency measurement technique of the encoder signals. The iterative formulation of the algorithm and the limited hardware requirements allows its implementation by means of a standard microcontroller (e.g., TMS320F24x) or by dedicated hardware. Communication between the smart sensor and the servo drive is preliminarily realized via high-speed serial peripheral interface.

Development of Quench Detection System for W7-X

The Quench Detection System of W7-X will consist of nearly 400 Quench Detection Units (QDU) for the fast and reliable supervision of the 70 superconducting coils and the 120 superconducting bus bar sections. There will be five control racks with about 80 QDU, a data acquisition unit, an ac–dc power supply with integrated dc UPS unit in each of the racks and a PC based data management system as an overlay structure. Each QDU will have a special analogue input circuit realised as a programmable half bridge front end with different polarity-sensing and limiting functions for suppressing high dynamic voltages. Special filter design is included for noise-suppression and over voltage protection. A reconfigurable control/arithmetic unit offers possibilities of future expansions (e.g. all digital evaluation). The QDU acquires and checks the differential voltages of the superconductors permanently. In case of a quench it triggers the fast discharge of the coils and the storage of the voltage signals on the memory unit. The quench signals are in the mV range and have to be clearly identified within a noisy and a high-voltage background within a few milliseconds. Each QDU transfers the stored signal dates via a high-speed RS485 serial interface with 20 kV optical isolation barrier to an industrial type data acquisition unit. A second optically isolated RS485-network enables interconnection of each QDU in the control rack (Compound-Mode of QDU). The QDU are designed with an internal failsafe, programmable self-test and redundancy feature, broken wire check of the quench detection cables and connectors inside and outside of the cryostat of W7-X. All QDU will be fed via an UPS supported 24 V dc bus through a high voltage isolated dc–dc transformer on each unit. The design of the Quench Detection System allows operation under high voltage levels of up to 8 kV and under magnetic stray field levels up to 30 mT. The front end is very well isolated and the outputs of the QDU are strictly separated by optical isolating transformers. The differential inputs are equipped with 500 V short-time over voltage protection. The paper gives an overview of the design of the first prototype.

A multi-frequency impedance analysing instrument for eddy current testing

This paper presents the design of a high-performance multi-frequency impedance analysing instrument (MFIA) for eddy current testing which has been developed primarily for monitoring a steel production process using an inductive sensor. The system consists of a flexible multi-frequency waveform generator and a voltage/current measurement unit. The impedance of the sensor is obtained by cross-spectral analysis of the current and voltage signals. The system contains high-speed digital-to-analogue, analogue-to-digital converters and dual DSPs with one for control and interface and one dedicated to frequency-spectra analysis using fast Fourier transformation (FFT). The frequency span of the signal that can be analysed ranges from 1 kHz to 8 MHz. The system also employs a high-speed serial port interface (USB) to communicate with a personal computer (PC) and to allow for fast transmission of data and control commands. Overall, the system is capable of delivering over 250 impedance spectra per second. Although the instrument has been developed mainly for use with an inductive sensor, the system is not restricted to inductive measurement. The flexibility of the design architecture is demonstrated with capacitive and resistive measurements by using appropriate input circuitry. Issues relating to optimizing the phase of the spectra components in the excitation waveform are also discussed.

43.2: A 400Mbps/ch SiDP Receiver for Mobile TFT-LCD Driver IC

A high speed serial interface receiver is realized in a 0.18um high voltage CMOS technology for a mobile 24-bit hVGA TFT-LCD driver (LDI) IC. The type of serial interface implemented is called Simple Display Port (SiDP) and is intended to replace the legacy RGB interface in the LDI IC's. The receiver consists of one clock and two data channels, and thereby reduces the number of signal lines going through the hinge of a mobile phone from 28 down to 6. All channels conform to Sub Low-Voltage Differential Signaling (SubLVDS) convention. The total transfer rate can be up to 800Mbps for two data channel. The current consumption was 5.4mA at the data rate of 600Mbps.