The Design of Serial ATA Bus Control Chip

Abstract

In a PC system, External storage interface is still a bottleneck in spite of its continuous improving performance, in contrast to the fast development of CPU, memory, graphic chips. The transfer rate in ATA protocol has been improved drastically from the beginning 3.3MB/s to current 133MB/s, but the plate electrode of a parallel interface is inevitably puzzled by clock skew, which limit the increasing of frequency and transfer rate can not be improved. Serial ATA protocol is compatible with Parallel ATA protocol in software layer. Its transfer rate is improved greatly due to serial interface with embedded clock. This paper will discuss the differences between Parallel ATA protocol and serial ATA protocol, and describe the hierarchical classification of serial ATA protocol model. Last a design for HPT183, a parallel/serial ATA bridge connection chip will be put forward. In high speed serial interface integrated circuit design, the design of high speed serial data recovery circuit is a troublesome task. In this paper an all-digital high speed serial data recovery circuit module for 1.5bps SATA interface implement is introduced. In contract to other design made from analog circuit, this all-digital circuit is an easily implement design and it has lower power consumption and smaller area. This circuit is being implemented in HPT183 chip which is designed and manufactured using a 0.18um CMOS process. At the end the test performance index for this chip is also provided.