High-speed Links Research Articles

A Novel CDR-Based Low-Cost Time-Interleaved-ADC Timing Calibration

Digital signal processing (DSP)-based system is a common architecture for high-speed communication links. One of the most important components for DSP-based architectures is the analog-to-digital convertor (ADC). Most of the high-speed ADCs are implemented as time interleaved ADC (TI-ADC). One of the major challenges in TI-ADC is the timing mismatch between the parallel sub-ADCs. The calibration of this mismatch increases system cost and complexity. In this article we propose a new background calibration method based on existing clock and data recovery (CDR) circuits. The timing mismatch can be calibrated using a simple and unique CDR per sub-ADC. Using the existing phase error detector and pulse gain estimator of the regular CDR, the calibration circuit becomes very low-cost, requiring only a first order loop, and a slow numerically controlled oscillator (NCO). VCSEL-based lab experiments are performed, which demonstrate the proposed method efficiency, performance and robustness.

A Novel Decision Feedback Equalization Structure for Nonlinear High-Speed Links

As the degree of nonlinearity in high-speed links becomes more and more serious, traditional decision feedback equalization (DFE) which is based on linear time-invariant assumption can no longer eliminate the inter-symbol interference effectively. In this paper, the shortcomings of traditional DFE structure for nonlinear high-speed links are first analyzed. Then, the multi-bit response (MBR) method is proposed to accurately construct the bit stream responses of the nonlinear high-speed links. Lastly, a novel DFE structure based on the MBR method is presented to improve the signal quality of the nonlinear high-speed links. The accuracy of the proposed method is verified by the simulation based on a nonlinear high-speed link model. Compared with traditional DFE, the proposed DFE structure can significantly improve the signal quality of the nonlinear high-speed links. As the degree of nonlinearity increases, the advantage of the proposed DFE becomes more prominent.

Support Vector Regression-Based Active Subspace (SVR-AS) Modeling of High-Speed Links for Fast and Accurate Sensitivity Analysis

A methodology based on the joint usage of support vector regression and active subspace is introduced in this paper for accelerated sensitivity analysis of high-speed links through parameter space dimensionality reduction. The proposed methodology uses the gradient directly obtained by support vector regression with Gaussian kernel to generate an active subspace with its application to the high-speed link model. Active subspace generated by this method is defined by the directions that are most influential on the desirable output measure. The resulting reduced-dimensional model is shown to perform well in sensitivity analysis of high-speed links including IBIS-AMI equalization, and is computationally more efficient than Sobol's method.

20-GS/s 8-bit Analog-to-Digital Converter and 5-GHz Phase Interpolator for Open-Source Synthesizable High-Speed Link Applications

Using digital standard cells and digital place-and-route (PnR) tools, we created a 20-GS/s, 8-bit analog-to-digital converter (ADC) for use in high-speed serial link applications with an ENOB of 5.6, a DNL of 0.95 LSB, and an INL of 2.39 LSB, which dissipated 175 mW in 0.102 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in a 16-nm technology. The design is entirely described in an HDL so that it can be ported to other processes with minimal effort and shared as open source.

SpiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System

SpiNNaker is a massively-parallel computer system optimized for the simulation, in real time, of very large networks of spiking neurons. The system consists of over 1 million, energy-efficient ARM cores distributed over 57,600 SpiNNaker chips, each of which contains 18 cores interconnected by a neurobiologically-inspired, asynchronous (clock-less) Network-on-Chip. The NoC is extended to the chip boundary for chip-to-chip communication. To construct the massively-parallel system, SpiNNaker boards, housing 48 SpiNNaker chips, are connected together using FPGA-based, high-speed serial links. This paper presents some of the novel aspects of the design and implementation of the bespoke interconnect, including a credit-based, reliable frame transport protocol that allows the multiplexing of asynchronous SpiNNaker channels over the serial links, and an efficient FPGA-to-SpiNNaker chip interface that provides twice the throughput of traditional asynchronous interfaces. SpiNNaker houses 3,600 Xilinx Spartan-6 FPGAs, provides a bisection bandwidth of 480 Gbit/s, and ran the first-ever, true real-time brain cortical simulation [1] - a feat not currently achievable using conventional HPCs or GPUs.

Basics of Clock and Data Recovery Circuits: Exploring High-Speed Serial Links

The choice of clock and data recovery (CDR) architecture in serial links dictates many of the blocklevel circuit specifications (specs). Block-level specs ultimately determine the energy efficiency of the system. Therefore, to design energy-efficient serial links, it is important to understand the basics of CDR operation, CDR's main performance metrics, and the relationship between circuit-level parameters and system-level performance metrics.

High Performance 128-Channel Acquisition System for Electrophysiological Signals

The increased popularity of investigations and exploits in the fields of neurological rehabilitation, human emotion recognition, and other relevant brain-computer interfaces demand the need for flexible electrophysiology data acquisition systems. Such systems often require to be multi-modal and multi-channel capable of acquiring and processing several different types of physiological signals simultaneously in realtime. Developments of modular and scalable electrophysiological data acquisition systems for experimental research enhance understanding and progress in the field. To contribute to such an endeavor, we present an open-source hardware project called High-Channel Count Electrophysiology or HiCCE, targeting to produce an easily-adaptable, cost-effective, and affordable electrophysiological acquisition system as an alternative solution for mostly available commercial tools and the current state of the art in the field. In this paper, we describe the design and validation of the entire chain of the HiCCE-128 electrophysiological data acquisition system. The system comprises of 128 independent channels capable of acquiring signal at 31.25 kHz, with 16 effective bits per channel with a measured noise level of about 3 μV. The reliability and feasibility of the implemented system have been confirmed through a series of tests and real-world applications. The modular design methodology based on the FPGA Mezzanine Card (FMC) standard allows the connection of the HiCCE-128 board to programmable system-on-chip carrier devices through the high-speed FMC link. The implemented architecture enables end users to add various high-response electrophysiological signal processing techniques in the field programmable gate arrays (FPGA) part of the system on chip (SoC) device on each channel in parallel according to application specification.

Gain analysis of high-speed DWDM link with different optical amplification configurations

Abstract Evolution of data-hungry devices has prompted the need for an exclusive communication infrastructure that can cater to the exponential increase in the need for high-speed data access. Since optical fiber links are inherently capable of supporting high-transmission data rates, fiber systems will be an integral part of the larger strategy to provide cost-effective high-speed data access to end users. This paper demonstrates the 100 × 40-Gbps dense wavelength division multiplexing (DWDM)-based 100-km-long fiber link whose performance has been analyzed using various configurations of a hybrid optical amplifier. The performance of the proposed link has been investigated using parameters like gain (dB) and bit error rate (BER). During the analysis, it has been observed that hybrid amplification, i.e., combination semiconductor optical amplifier (SOA), erbium-doped fiber amplifier (EDFA), and Raman amplifier, delivers overwhelming gain (dB) in comparison to the conventional stand-alone amplifier. Further, it has been seen that among different positional configurations of the amplifier, symmetrically positioned hybrid amplifiers achieved the gain of 18.6 dB, while the SOA link with similar configuration and parameters delivered link gain of merely −2.6 dB. In terms of BER performance, the symmetric hybrid configuration was outstanding with BER of 10−5, while preamplification link BER was merely 10−3, and post amplification being the most undesirable. The proposed link has been designed and investigated using OptiSystemTM 14.2.

Management and Equalization of Energy Storage Devices for DC Microgrids Using a SoC-Sharing Function

This paper presents a method for Energy Storage Systems (ESSs) equalization and energy management in dc microgrids (MGs) with slow dynamic sources, such as Fuel Cells (FCs). The three main features of this method are the ESSs equalization, the energy management between the ESSs and the FC, and the ability to suppress fast transients of load, preventing damages in the FC. The equalization is performed using a State of Charge ( $SoC$ )-Sharing Function, which is based on a Sigmoid Function (SF). The $SoC$ -Sharing Function is designed similarly to the droop controller, therefore, it is suitable for operation in droop based MGs. Additionally, the ability to suppress fast transients of load is performed by adding a low pass filter in the FC control loop. The main advantages of this method are the SF smooth behavior and the lack of need for a high-speed link of communication between the sources. To evaluate the MG stability, the Lyapunov’s Indirect Method is applied in the MG model considering different scenarios varying the $SoC$ and load connected to the dc-link. Finally, the model is validated by comparing simulation and experimental results supplied by a lab-scale prototype.

Secondary Side-Channel Wireline Communication Using Transmitter Clock Frequency Modulation

A secondary communication link, or side-channel, is proposed, which uses binary frequency shift keying to modulate the frequency of a high-speed wireline transmitter clock. This side-channel data is then received using the corresponding receiver’s conventional clock and data recovery (CDR) circuit. An analysis of the CDR loop parameters demonstrates that, within certain limits, the side-channel does not impact the signal integrity of the primary high-speed data. Measurements were made on a side-channel prototype using a 56-Gb/s PAM-4 (half-rate 14-GHz clock) transceiver in 7-nm FinFET technology through a 15-dB loss channel. Over 104 side-channel bits were transmitted at 50 kb/s, and the side-channel remained error-free with no visible impact on the high-speed link.

Methodology for Digital Synthesis of Deterministic and Random Jitter Generation on Rising or Falling Edges of Data Pattern

Jitter is becoming an important factor in high-speed serial link and integrated circuits (ICs). Generating controllable jitter plays a crucial role in simulating the test environment of high-data links, evaluating the performance of IC, preventing jitter in high-speed serial link, and even testing the synchronous trigger circuit. In this paper, a digital synthesis for jitter generation and a logical combination method for selecting jitter on the rising edge or falling edge of a data pattern are presented. Precisely controllable jitter is generated by digital synthesis, including sinusoidal period jitter, rectangular period jitter, duty cycle distortion (DCD) jitter, and adjustable random jitter. Additionally, the validity and accuracy of the proposed method were demonstrated by hardware experiments, where the jitter frequency had an accuracy of ±30 ppm and the jitter amplitude had a step of 2 ps.

FPGA-Accelerated 3rd Generation DNA Sequencing.

DNA measurement machines are undergoing an orders-of-magnitude size and power reduction. As a result, the analysis of genetic molecules is increasingly appropriate for mobile platforms. However, sequencing these measurements (converting to the molecule's A-C-G-T text equivalent) requires intense computing resources, a problem for potential realizations as mobile devices. This paper proposes a step towards addressing this issue, the design and implementation of a low-power real-time FPGA hardware accelerator for the basecalling task of nanopore-based DNA measurements. Key basecalling computations are identified and ported to a custom FPGA which operates in tandem with a CPU across a high-speed serial link and a simple API. A measured speed-up over CPU-only basecalling in excess of 100X is realized with an energy efficiency improvement of three orders of magnitude.

Enhanced performance of indoor VLC using anti-periodic asymmetrically clipped OFDM and multiple LEDS

Visible light communication (VLC) systems make use of the available LED lamps to realize a high spatial density of high-speed optical links superposed to their natural illumination function. Orthogonal frequency division multiplexing (OFDM) has been adopted for these intensity modulation/direct-detection optical channels. However, it suffers from low power efficiency or low spectral efficiency. In this paper, we aim to improve the performance of OFDM-based indoor VLC systems. By utilizing the principle of spatial summing, we propose an anti-periodic asymmetrically clipped OFDM scheme to make efficient use of both power and spectrum. In this scheme, the OFDM subcarriers are partitioned into multiple specific groups to form independent unipolar signals. These signals are simultaneously transmitted from different LEDs that are within the same light fixture and are summed in space before being detected by a conventional OFDM receiver. The computer simulation results show that the proposed approach can achieve lower PAPR and more robustness to the clipping distortion caused by the nonlinearities of LED leading to better bit error rate performance for the same spectral efficiency than that of the conventional DCO-OFDM and ACO-OFDM schemes do under both LOS and DOW channels.

Performance of grey‐coded IQM‐based optical modulation formats on high‐speed long‐haul optical communication link

In this article the performance of grey-coded advanced optical modulation formats is evaluated on a single-channel high-speed long-haul optical communication link and are compared to the respective differential-coded modulation formats. Polarisation division multiplexed optical in-phase quadrature modulator (IQM) structure and homodyne detection scheme are used to realise 100 Gbps quadrature phase-shift keying (QPSK), 120 Gbps 16-ary quadrature amplitude modulation (16-QAM), 360 Gbps 32-QAM and 480 Gbps 64-QAM modulation formats. Advanced digital signal processing unit with various pre-processing and recovery stages such as direct current blocking, normalisation, low-pass Bessel filter, resampling, quadrature imbalance compensation, chromatic dispersion compensation, non-linear compensation, timing recovery, adaptive equalisation, down-sampling, frequency offset estimation, and carrier phase estimation is used at the receiving end to compensate for signal impairments during propagation. Maximum transmission distances of 7200, 1050, 560, and 360 km have been achieved at an acceptable bit error rate for QPSK, 16-QAM, 32-QAM, and 64-QAM, respectively. The grey-coded systems outperformed the differential-coded systems regarding optical signal-to-noise ratio requirement, receiver sensitivity, and transmission distance.

Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation

This paper presents a statistical model to accurately estimate post-FEC BER for high-speed wireline links using standard linear block codes, such as the RS(544,514,15) KP4 and RS(528,514,7) KR4 codes. A hierarchical approach is adopted to analyze the propagation of PAM-symbol and FEC-symbol errors through a two-layer Markov model. A series of techniques including state aggregation, time aggregation, state reduction, and dynamic programming are introduced making the time complexity to compute post-FEC BER below 10−15 reasonable. Error bounds associated with each method are found. The efficiency of the proposed model allows it to handle a larger state space, more DFE taps, and more sophisticated linear block codes than prior work. A 4-PAM 60 Gb/s wireline transceiver fabricated in a 7 nm FinFET technology is used as a test vehicle to validate this model. Measured data with two different channels reveals that the statistical model can properly predict the post-FEC error floor with standard FEC codes. While this paper demonstrates the method for capturing DFE error propagation, the method is general and can be applied to model other communication systems having memory effects. Moreover, our proposed model can be easily extended to higher-level PAM schemes and other advanced equalizer architectures to assist in making architectural choices for wireline transceivers.

A Generic High Bandwidth Data Acquisition Card for Physics Experiments

In high energy physics and nuclear physics experiments, particularly the ones based on a particle accelerator, the data rate from the detector is usually in the order of terabytes per second. These high throughput data from detector front-end electronics (FEEs) need to be transmitted to the back-end computing farm for high-level event selection and building. A data acquisition (DAQ) system with the features of high density, scalable, and easily upgradeable is crucial to simplify the readout architecture of the whole experiment. This article will introduce the design of a generic high bandwidth PCIe card, which can be used as the important input-output card in a scalable DAQ system. It can factorize FEEs from data handling and reduce the amount of custom hardware in favor of scalable detector-independent commercial hardware and software. Besides the 48 channels of bidirectional high-speed fiber optical links with front ends, it also supports to synchronize with the experiment timing system and to fan-out the clock and trigger information with a fixed latency to the FEEs.

Design of airborne target tracking accelerator based on KCF

The on-board target tracking of unmanned aerial vehicle (UAV) relies on on-board computer to process the collected ground image information, and then use the target tracking algorithm to achieve the target tracking function, which provides the user with target position, trajectory and other information. UAVs are limited by load and power consumption. Due to the high resolution and frame rate of UAV's image collection system, traditional target tracking platforms cannot meet the requirements. As a result, the real-time nature of the tracking platform urgently needs to be resolved. This study designs and implements the airborne ground target tracking accelerator for UAV. The kernelised correlation filters (KCFs) algorithm with low computational complexity and precision is selected to achieve the airborne ground target tracking function and its performance bottleneck is analysed. In order to improve the real-time performance of the tracking task processing, the ZYNQ platform based on ARM and field programmable gate arrays is chosen to achieve the hardware acceleration of the KCF algorithm. The KCF algorithm is implemented in hardware using the high-level synthesis technology, and a high-speed data transmission link is established. Experiments show that the design can achieve a tracking rate of more than 30 FPS under 960 × 540 resolution, which meets the real-time requirements of UAV target tracking task.

Development of high-speed FSO transmission link for the implementation of 5G and Internet of Things

Internet of Things (IoT) enables the inter-connectivity of different “things” using which wide range of items and devices can communicate with each other and their external environment. 5G technology offers enhanced quality of service with high-data transmission rates, which necessitates the implementation of IoT in 5G architecture. Free space optics (FSO) is considered as a promising technology that can offer high-speed information transmission links and therefore is an optimal choice for wireless networks to satisfy the full potential of 5G technology offering 100 Gbit/s or more speed. By implementing 5G features in IoT, the coverage area and performance of IoT will be enhanced using high-speed FSO links. This work proposes the development of high-speed long-reach FSO link for the implementation of 5G and IoT. We investigate a long-haul, single-channel polarization division multiplexed 16-level quadrature amplitude modulation (PDM-16-QAM) based FSO link at 160 Gbit/s incorporating digital signal processing with coherent detection at the receiver terminal. The results show that the proposed system demonstrates a good bit error rate performance under different weather conditions. The proposed system can be deployed for high-speed, long-haul, spectral efficient, robust information transmission links in future 5G wireless networks under dynamic weather conditions.

Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs

The usage of SRAM-based Field Programmable Gate Arrays on High Energy Physics detectors is mostly limited by the sensitivity of these devices to radiation-induced upsets in their configuration. These effects may alter the functionality until the next reconfiguration of the device. In this work, we present the radiation testing of a high-speed serial link hardened by a new, custom scrubber designed for Xilinx FPGAs. We compared the performance of our scrubber to the Xilinx Single Event Mitigation (SEM) controller and we measured the impact of the scrubbers on the reliability of the link. Our results show that our scrubber may improve reliability up to 23 times over the SEM.

Ultraviolet-to-blue color-converting scintillating-fibers photoreceiver for 375-nm laser-based underwater wireless optical communication

Underwater wireless optical communication (UWOC) can offer reliable and secure connectivity for enabling future internet-of-underwater-things (IoUT), owing to its unlicensed spectrum and high transmission speed. However, a critical bottleneck lies in the strict requirement of pointing, acquisition, and tracking (PAT), for effective recovery of modulated optical signals at the receiver end. A large-area, high bandwidth, and wide-angle-of-view photoreceiver is therefore crucial for establishing a high-speed yet reliable communication link under non-directional pointing in a turbulent underwater environment. In this work, we demonstrated a large-area, of up to a few tens of cm2, photoreceiver design based on ultraviolet(UV)-to-blue color-converting plastic scintillating fibers, and yet offering high 3-dB bandwidth of up to 86.13 MHz. Tapping on the large modulation bandwidth, we demonstrated a high data rate of 250 Mbps at bit-error ratio (BER) of 2.2 × 10-3 using non-return-to-zero on-off keying (NRZ-OOK) pseudorandom binary sequence (PRBS) 210-1 data stream, a 375-nm laser-based communication link over the 1.15-m water channel. This proof-of-concept demonstration opens the pathway for revolutionizing the photodetection scheme in UWOC, and for non-line-of-sight (NLOS) free-space optical communication.