SpiNNlink: FPGA-Based Interconnect for the Million-Core SpiNNaker System

Luis A Plana,Jim Garside,Jonathan Heathcote,Simon Davidson,Mikel Lujan,Jeffrey Pepper,Steve Furber,Steve Temple

doi:10.1109/access.2020.2991038

Luis A Plana, Jim Garside + Show 6 more

Open Access

https://doi.org/10.1109/access.2020.2991038

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Abstract

SpiNNaker is a massively-parallel computer system optimized for the simulation, in real time, of very large networks of spiking neurons. The system consists of over 1 million, energy-efficient ARM cores distributed over 57,600 SpiNNaker chips, each of which contains 18 cores interconnected by a neurobiologically-inspired, asynchronous (clock-less) Network-on-Chip. The NoC is extended to the chip boundary for chip-to-chip communication. To construct the massively-parallel system, SpiNNaker boards, housing 48 SpiNNaker chips, are connected together using FPGA-based, high-speed serial links. This paper presents some of the novel aspects of the design and implementation of the bespoke interconnect, including a credit-based, reliable frame transport protocol that allows the multiplexing of asynchronous SpiNNaker channels over the serial links, and an efficient FPGA-to-SpiNNaker chip interface that provides twice the throughput of traditional asynchronous interfaces. SpiNNaker houses 3,600 Xilinx Spartan-6 FPGAs, provides a bisection bandwidth of 480 Gbit/s, and ran the first-ever, true real-time brain cortical simulation [1] - a feat not currently achievable using conventional HPCs or GPUs.

Highlights

Understanding how the brain works is one of the outstanding scientific grand challenges
Due to the independent operation of the SpiNNaker channels and their unpredictable traffic patterns, a global credit value for the High-Speed Serial Links (HSSLs) is inefficient, as the packet dispatcher (PD) would have to re-credit frame assembler (FA) based on the packet FIFO with fewer available slots
SUMMARY AND CONCLUSIONS The million-core SpiNNaker computer is capable of running brain cortical simulations in true real-time, not currently possible using conventional HPCs or GPUs

Summary

Introduction

Understanding how the brain works is one of the outstanding scientific grand challenges. FA consumes credit with every assembled frame and is re-credited by the remote PD based on the occupancy of its FIFOs. due to the independent operation of the SpiNNaker channels and their unpredictable (spike) traffic patterns, a global credit value for the HSSL is inefficient, as the PD would have to re-credit FA based on the packet FIFO with fewer available slots.

Results

Conclusion