Abstract
High bit rate, high density, low power consumption, low voltage and high current are among the major features and demands of today’s high-speed serial link among ICs/chiplets mounted on an interposer. With the development of serial link subsystem towards higher throughput, the data transmission rate has increased significantly. The validation of the design for high-speed serial links concerning signal integrity and power integrity has brought great challenges to engineers at home and abroad. There is still plenty of room in the studies relating to process optimization, measurement/analysis and system design of TSV (through silicon via) enabled silicon interposer. Interconnect elements such as TSVs and RDLs (redistribution layer) present non-ideal factors that impact negatively on the signal integrity and power integrity of serial links among ICs on an active interposer. In this paper, we first introduce the passive interconnection composed of TSV/RDL and their equivalent circuit model. Then, we use a compact modeling method to simulate the whole high speed serial full-link, in order to reveal the behavior of the data transmission and signal quality. The modeling and simulation results for high-speed serial links per various PICe specs are revealed, based on commercial tools, such as ADS (Advanced Design System) software.
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