Abstract
This paper presents a statistical model to accurately estimate post-FEC BER for high-speed wireline links using standard linear block codes, such as the RS(544,514,15) KP4 and RS(528,514,7) KR4 codes. A hierarchical approach is adopted to analyze the propagation of PAM-symbol and FEC-symbol errors through a two-layer Markov model. A series of techniques including state aggregation, time aggregation, state reduction, and dynamic programming are introduced making the time complexity to compute post-FEC BER below 10−15 reasonable. Error bounds associated with each method are found. The efficiency of the proposed model allows it to handle a larger state space, more DFE taps, and more sophisticated linear block codes than prior work. A 4-PAM 60 Gb/s wireline transceiver fabricated in a 7 nm FinFET technology is used as a test vehicle to validate this model. Measured data with two different channels reveals that the statistical model can properly predict the post-FEC error floor with standard FEC codes. While this paper demonstrates the method for capturing DFE error propagation, the method is general and can be applied to model other communication systems having memory effects. Moreover, our proposed model can be easily extended to higher-level PAM schemes and other advanced equalizer architectures to assist in making architectural choices for wireline transceivers.
Highlights
F ORWARD error correction (FEC) has become an integral part of many wireline links at data rates above 25 Gb/s whose impact must be considered when architectingManuscript received June 14, 2019; revised August 29, 2019; accepted September 20, 2019
Instead of using the FEC limit paradigm currently employed by many designs [4]–[6], which doesn’t consider decision feedback equalization (DFE) error propagation, a model that accurately predicts very low post-FEC BERs is important for modern SerDes design
This paper described a systematic and efficient method that can be used to accurately estimate post-FEC BER for high-speed wireline communication channels using standard linear block codes on GF(2m)
Summary
F ORWARD error correction (FEC) has become an integral part of many wireline links at data rates above 25 Gb/s whose impact must be considered when architecting. Ref [12] explains the approach in the IEEE 10GBASE standard for handling DFE error propagation It considers bursts combining correct and erred bits, and enumerates all possible burst-error patterns to estimate BER and link performance. This time-consuming approach is ill-suited to the longer linear block codes adopted in recent wireline standards [13], [14]. Our proposed BER estimation method for wireline links is an extension of [16], and provides a set of tools to assist in making architectural choices for wireline transceivers, such as co-design of the equalization and FEC in the presence of DFE error propagation and various noise sources.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
