Abstract
A secondary communication link, or side-channel, is proposed, which uses binary frequency shift keying to modulate the frequency of a high-speed wireline transmitter clock. This side-channel data is then received using the corresponding receiver’s conventional clock and data recovery (CDR) circuit. An analysis of the CDR loop parameters demonstrates that, within certain limits, the side-channel does not impact the signal integrity of the primary high-speed data. Measurements were made on a side-channel prototype using a 56-Gb/s PAM-4 (half-rate 14-GHz clock) transceiver in 7-nm FinFET technology through a 15-dB loss channel. Over 104 side-channel bits were transmitted at 50 kb/s, and the side-channel remained error-free with no visible impact on the high-speed link.
Highlights
In high-speed wireline communication links, limited channel bandwidth requires equalization in the transmitter (TX) and receiver (RX) to compensate for frequency-dependent loss [1]
Whereas in [10], clock phase modulation introduced additional jitter to the high-speed link, we show in Section III that by respecting specific limits of the clock and data recovery (CDR), the binary frequency shift keying (BFSK) side-channel will not impact on the high-speed data’s signal integrity
A prototype of the proposed side-channel link is tested on a 7-nm FinFET 56 Gb/s PAM-4 transceiver from [2]
Summary
In high-speed wireline communication links, limited channel bandwidth requires equalization in the transmitter (TX) and receiver (RX) to compensate for frequency-dependent loss [1]. A secondary communication link, i.e., a backchannel, would be required to permit the RX to transmit control bits embedding information, such as ISI, channel response, BER, process variation, and temperature back to the TX. While this can be implemented with another physical channel [6], the cost of increasing pin count is very high. In [10], a secondary channel is created by modulating the TX clock phase to transmit additional data While this method alleviates the drawbacks in [7] and [8], it requires injecting a large phase shift outside the RX clock and data recovery (CDR) circuit’s tracking bandwidth for the secondary data to be visible. Without modifying the primary data, the proposed side-channel architecture creates a low-speed and nondisruptive secondary channel for communication between the high-speed physical-layer TX and RX
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