Abstract
Conventional clock and data recovery (CDR) using a phase locked loop (PLL) suffers from problems such as long lock time, low frequency acquisition and harmonic locking. Consequently, a CDR system using a time to digital converter (TDC) is proposed. The CDR consists of simple arithmetic calculation and a TDC, allowing a fully digital realization. In addition, utilizing a TDC also allows the CDR to have a very wide frequency acquisition range. However, deterministic jitter is caused with each sample, because the system's sampling time period is changing slightly at each data edge. The proposed system does not minimize jitter, but it tolerates small jitter. Therefore, the system offers a faster lock time and a smaller sampling error. This proposed system has been verified on system level in a Verilog-A environment. The proposed method achieves faster locking within just a few data bits. The peak to peak jitter of the recovered clock is 60 ps and the RMS jitter of the recovered clock is 30 ps, assuming that the TDC resolution is 10 ps. In applications where a small jitter error can be tolerated, the proposed CDR offers the advantage of fast locking time and a small sampling error.
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