Abstract
Jitter is becoming an important factor in high-speed serial link and integrated circuits (ICs). Generating controllable jitter plays a crucial role in simulating the test environment of high-data links, evaluating the performance of IC, preventing jitter in high-speed serial link, and even testing the synchronous trigger circuit. In this paper, a digital synthesis for jitter generation and a logical combination method for selecting jitter on the rising edge or falling edge of a data pattern are presented. Precisely controllable jitter is generated by digital synthesis, including sinusoidal period jitter, rectangular period jitter, duty cycle distortion (DCD) jitter, and adjustable random jitter. Additionally, the validity and accuracy of the proposed method were demonstrated by hardware experiments, where the jitter frequency had an accuracy of ±30 ppm and the jitter amplitude had a step of 2 ps.
Highlights
Jitter is becoming an important factor in high-speed serial links and integrated circuits (ICs)
Jitter generation can perform jitter tolerance measurements by generating quantized controllable jitter and injecting different types of jitter into the incoming high-speed data stream, detect the bit error rate (BER) of the code stream transmitted in the channel, and verify the ability of the receiver clock data recovery (CDR) while maintaining performance levels [8,9]
This paper proposes a full digital synthesis method that achieves controllable jitter generation
Summary
New high-speed serial data standards are emerging, such as universal serial bus (USB) and the peripheral components interconnect express (PCIE). These serial standards are more susceptible to jitter and greatly cause bit error rate (BER) [1,2], and with them the requirement for effective compliance and characterization measurement [3,4]. As data rates for new generation IC continue increases, jitter injected module (JIM) is intended to generate controllable jitter, simulating the test environment of high-data links and evaluating the performance of IC [5,6,7]. It can be used to simulate the test environment of high-data links while evaluating the performance of the integrated circuit or system [5,6,7]; be used in CSC spread spectrum to reduce interference [10], improve the linearity of the CDR phase detector (PD) [11]; and measure the input of the phase interpolator for measuring the correlation jitter between data signal and CDR [12] and timing specifications for routers, gateways, or digital subscriber line access multiplexers (DSLAMs) [13]
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