High-speed Full Adder Research Articles

An Approach to Design a Low Power High-Speed Full Adder Circuit Based on Logical Effort

An Approach to Design a Low Power High-Speed Full Adder Circuit Based on Logical Effort

Role of tuning techniques in advancing the performance of negative capacitance field effecting based full adder

<p>The increasing demand for faster, robust, and efficient device development of enabling technology to mass production of industrial research in circuit design deals with challenges like size, efficiency, power, and scalability. This paper, presents a design and analysis of low power high speed full adder using negative capacitance field effecting transistors. A comprehensive study is performed with adiabatic logic and reversable logic. The performance of full adder is studied with metal oxide field effect transistor (MOSFET) and negative capacitance field effecting (NCFET). The NCFET based full adder offers a low power and high speed compared with conventional MOSFET. The complete design and analysis are performed using cadence virtuoso. The adiabatic logic offering low delay of 0.023 ns and reversable logic is offering low power of 7.19 mw.</p>

Novel Design of Ripple Carry Adder using High Speed 12T Hybrid MOS Transistors

This paper designs and extends a high speed full adder using 12 MOS Transistors to a ripple carry adder (RCA). The proposed design reduces delay and is effective for Power Delay Product (PDP). Using both complementary MOSFET (CMOS) logic and complementary pass transistor logic(CPL), a new 6T XNOR full adder(FA) is created. CPL is used in the design for Carry and Sum logic in order to minimise circuit delay. The proposed work has a delay of 11.86 ps and a PDP of 0.368fj. By using a newly proposed single bit adder, a 4-bit Ripple Carry Adder(RCA) is designed with 1.2 v supply yielding a power of 572.063uw, delay 0.32ns and PDP 183.06 fj. The outcomes obtained are compared with existing models. For characterstics of speed and PDP, the proposed model outperforms existing models significantly. The circuit was designed in 90nm GPDK technology by using the CADENCE VIRTUOSO TOOL.

A low-power high speed full adder cell using carbon nanotube field effect transistors

The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.

Booth Multiplier Based on Low Power High Speed Full Adder With Fin_FET Technology

This paper proposes a novel Fin FET-based HSFA for the multiplier in order to overcome the issues of low speed operation. It is advantageous to use Fin FETs to construct the arithmetic circuit while assessing the available works. The carry propagation and slow operation of the old technique are disadvantages. The CMOS-based compressor circuit, on the other hand, suffers from leakage current, which reduces its driving capabilities. High current DSP applications are well matched to the design's specifications. Even with a supply voltage of 1 volt, the proposed device has a decent driving capability. As a result, the circuit runs more quickly and has less latency. A transmission gate is used in the design of the suggested adder structure to selectively block or transfer data from the input to output. Half adder and adder are shown in the following illustrations. The smaller the transistor count, the less power it uses. The suggested Fin FET design for the smaller transistors has a superior driving capability than the CMOS equivalent. Additionally, when cascading, the Fin FET based adder may contribute to superior switch performance, such as when using ripple carry adder. There is also the possibility of a low operation, which may operate at Low wattage Electronic designs for high-performance and small devices have become increasingly dependent on the use of VLSI circuits. The power of a processor is determined in large part by the multiplier used in its design. Multiplier factor booth coding is being used to reorder the input bits in order to reduce facility use. The booth decoder works by rearranging the specified booth equivalent. The Booth decoder has the ability to expand the range of zeros. As a result, the power consumption of the design will be decreased even more. As soon as the input bit constant drops below zero, related rows or columns of an adder must be disabled, if possible.

Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder

Background: Full adder is the key element of digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder, CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with a new Gate diffusion technique has been implemented in this work. This is a comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultra-low-power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit. Moreover, it also reduces the number of transistors required. This technique has been used with CNTFET to upgrade the full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The FinFET design also shows the better performance with GDI. But GDI enhances CNTFET based design power consumption by about 32% from the FinFET. Conclusions: CNTFET showed a better response due to good current conductivity as compared to the FinFET. This work has been implemented and simulated on the 32nm node technology.

Ultra high speed full adder for biomedical applications

In the field of bio medical engineering high performance CPU for digital signal processing plays a significant role. Frequency efficient circuit is a paramount requirement for the portable digital devices employing various digital processors. In this work a novel high speed one-bit 10T full adder with complemented output was described. The circuit was constructed with XOR gates which were built using two CMOS transistors. The XOR gate was constructed using 2T multiplexer circuit style. It was observed that power consumption of the designed circuit at 180nm with supply voltage 1.8V is 183.6 uW and delay was 1.809 ps whereas power consumption at 90nm with supply voltage 1.2V is 25.74 uW and delay was 8.245 ps. The observed Power Delay Product (PDP) in 180nm (at supply voltage 1.8V) is 0.33 and in 90nm (at supply voltage 1.2V) is 0.212. The work was extended by implementing a 32-bit Ripple Carry Adder (RCA) and was found that the delay at 180nm is 93.7ps and at 90nm is 198ps. The results were drawn at 180nm and also 90nm technology using CAD tool. The results say that the present work offered significant enhancement in speed and PDP compared with existing designs.

Design of area-efficient high speed 4 × 4 Wallace tree multiplier using quantum-dot cellular automata

Complementary metal oxide semiconductor (CMOS) devices are expected to face new challenges such as exponential current leakage, DIBL, hot carrier effects, and etc. at nano scale. Hence the CMOS technology is being supplanted by the nanotechnologies. Quantum-dot Cellular Automata (QCA) is key technology at nano scale which operates at tera hertz of speed. Comparing with the traditional CMOS technology, the QCA technology has low power consumption and high density. This technology also has a unique methodology such as “processing in wire” and “memory-in-motion”. This work confers an area proficient, high speed full adder (FA) design with efficient clocking. The proposed full adder design comprises of 26 Quantum cells with delay of two clock phases, area occupancy of 0.03 µm 2 . This paper utilizes the unique characteristics of QCA and the proposed Wallace tree multiplier is implemented with the mentioned FA and is designed by using QCA Designer 2.0.3 tool.

HIGH SPEED ADDER USING GDI TECHNIQUE

Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

A Novel high-speed low power 9T full adder

In modern era, low power high speed applications become one of the prime areas of focus for digital VLSI applications. Addition is a vital arithmetic operation and it acts as the main building block for synthesizing all other operations. A low power high speed full adder is introduced using 9 transistors. It consists of 3 modules, XOR module, sum module and carry module. While comparing with other designs it has a significant reduction in delay, power and hence the power delay product. The circuit is implemented and simulated using Cadence Virtuoso tool. Entire design is divided into three modules. Module 1 consists of modified XOR circuit which has only four transistors. Module 2 and Module 3 are SUM and CARRY design respectively. CARRY OUT of full adder circuit is made up by using Gate Diffusion Input (GDI)logic whereas the SUM is made using another XOR design. The design was implemented using cadence tool and power, delay and PDP are found to be very small as compared with otherdesigns.

A novel energy-efficient and high speed full adder using CNTFET

In the present paper, we will present two high speed, energy efficient and low power full adder circuits using gate diffusion input (GDI) cell, semi XOR/XNOR modules and carbon nanotube field effect transistors (CNTFET). Due to unique electrical and mechanical features of CNTFET, it can be chosen as an appropriate alternative to replace the metal oxide field effect transistors (MOSFET). In order to evaluate several figures of metric (FOM) including power consumption, energy consumption, propagation delay and energy delay product (EDP) using different voltage supplies, load capacitances, temperatures, frequencies and tubes, extensive experiments of proposed designs and previous works will be presented. Comparing to the previous works, simulation results of HSPICE illustrate the superiority of proposed designs regarding propagation delay and EDP.

Novel High-Efficient Full Adder Cell Based on Bootstrapped Structure

This paper presents a comparative research of low-power and high-speed full adder cells which are based on XOR-XNOR algorithm. The adder cells are decomposed into small modules and all of them have an in-depth analysis. Several designs of each of them are implemented, optimized, simulated and analyzed separately. We also design a novel XORXNOR module built upon bootstrapped pass transistor logic use silicon on insulator (SOI) process with the characteristics of the full voltage swing at internal nodes and low shortcircuit current which helps in reducing the power-delay product (PDP) for high performance applications. Many different full adder cells are constructed with different XOR-XNOR modules. A realistic test environment with buffers and loads are used for simulation. All full adder cells were simulated by HSPICE based on 130 nm CMOS technology at 1.2 V supply voltages. Four sets of frequencies were operated: 25 MHz, 50 MHz, 100 MHz and 200 MHz with 50% duty cycle at four different load capacitances. A comprehensive comparison and analysis are also carried out to test the performance of the adders. Each of these cells shows different performances in terms of power consumption, speed, and PDP. The simulation results of this research are expected to help designers to select the appropriate full adder cell that satisfies their specific applications.

Design of High Speed Full Adder using Improved Differential Split Logic Technique for 130nm Technology and its Implementation in making ALU

Adders are the main components in digital designs which are used not only for addition but can be used for multiplication and division too. Adders find use in very large scale integrated circuits from processors (like in arithmetic logic circuits) to application specific integrated circuits. At the same time, high speed computation has become the important part of any digital applications today though low power is a key factor too. In this paper, a high speed full adder using improved differential split logic (DSL) technique is used. We further implement it in 1bit arithmetic logic circuit (ALU). Measurements show that proposed full adder is better than DSL full adder in terms of speed, and further implementation of it in ALU shows that it is better than CMOS ALU in terms of speed, power and power delay product (PDP). General Terms Full adder, Differential split level logic (DSL), Differential cascade voltage logic (DCVS), Arithmetic logic circuit (ALU), Power delay product (PDP), Full adder (FA), Multiplexer (Mux).

Synthesis of High Speed Full Adder

Synthesis of High Speed Full Adder

High Speed Full Adder Based on Modified Linear Threshold Gate and Its Application to a 4–2 Compressor

High Speed Full Adder Based on Modified Linear Threshold Gate and Its Application to a 4–2 Compressor

Low‐power high‐speed full adder for portable electronic applications

A low-power, high-speed full adder (FA), abbreviated as LPHS-FA, is presented as an elegant way to reduce circuit complexity and improve the performance thereof. Employing as few as 15 MOSFETs in total, an LPHS-FA requires 60-73% fewer transistors than other existing FAs with drivability. For validation purpose, HSPICE simulations are conducted on all the proposed and referenced FAs based on the TSMC 0.18-μm CMOS process technology. The LPHS-FA is found to provide a 20.4-21.2% power saving, a 12.3-67.0% delay time reduction and a 35-102% reduction in power delay product compared with the referenced FAs. In short, an LPHS-FA is presented in a concise form as a high-performance FA in practical applications.

A Novel High Speed Full Adder Based on Linear Threshold Gate and its Application to a 4-2 Compressor

This paper proposes a novel full adder based on the linear threshold gate (LTG) which belongs to the single-electron-device (SED) family. The advantage of an LTG-based circuit is that it has a satisfactory fan-out as opposed to other SED-based circuits; hence, it can be utilized in any complex circuit network. The proposed full adder is utilized as an application in a 4-2 compressor architecture. Compressors are elementary building blocks which are widely used in arithmetic structures such as multipliers. The proposed 4-2 compressor can operate reliably in any tree structured parallel multiplier due to its high performance full adders. The SIMON simulator demonstrates the correct operation of the proposed full adder design, along with the presented 4-2 compressor. The performance of proposed full adder and the 4-2 compressor, in terms of delay and power consumption, are calculated in complete detail. The comparisons indicate that the proposed full adder has the highest speed in comparison with the previous high speed designs.

High Speed Multiple Valued Logic Full Adder Using Carbon Nano Field Effect Transistor

High speed Full-Adder (FA) module is a critical element in designing high performance arithmetic circuits. In this paper, we propose a new high speed multiple-valued logic FA module. The proposed FA is constructed by 14 transistors and 3 capacitors, using carbon nano-tube field effect transistor (CNFET) technology. Furthermore, our proposed technique has been examined in different voltages (i.e., 0.65v and 0.9v). The observed results reveal power consumption and power delay product (PDP) improvements compared to existing FA counterparts

High-speed full adder based on minority function and bridge style for nanoscale

In this paper a new high-speed and high-performance Full Adder cell, which is implemented based on CMOS bridge style and minority function, is proposed. Several simulations conducted at nanoscale using different power supplies, load capacitors, frequencies and temperatures demonstrate the superiority of the proposed design in terms of delay and power-delay product (PDP) compared to the other cells. In addition the proposed structure improves the robustness and reduces sensitivity to the process variations of the other Bridge-Cap Full Adder cell already presented in the literature.

High Speed Capacitor-Inverter Based Carbon Nanotube Full Adder

Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed Full Adder cell. In this paper, we present a high speed Full Adder cell using CNFETs based on majority-not (Minority) function. Presented design uses eight transistors and eight capacitors. Simulation results show significant improvement in terms of delay and power-delay product in comparison to contemporary CNFET Adder Cells. Simulations were carried out using HSPICE based on CNFET model with 0.6 V VDD.