Abstract
Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.
Highlights
In many of the VLSI applications such as Digital Image Processing (DSP), microprocessors and many more, we see the substantial use of adders
Researchers have come up with different full adder designs that can bring about systems with high performance and low power utilization
The drawback of Complementary Pass transistor logic (CPL) full adder is that the number of transistors used is more
Summary
In many of the VLSI applications such as Digital Image Processing (DSP), microprocessors and many more, we see the substantial use of adders. The arithmetic operations such as addition, subtraction, division, multiplication are all performed with the help of adders. Researchers have been extensively working on designing low power systems as it has been a major design parameter days. Researchers have come up with different full adder designs that can bring about systems with high performance and low power utilization. [Adekanmbi et al, Vol. (Iss.: SE): February, 2018] [Communication, Integrated Networks & Signal Processing-CINSP 2018]
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