High Power GaN Research Articles

Methodology for predicting off-state reliability in GaN power transistors

Results of a lifetest across temperature and drain voltage on off-state high power GaN FET test structures are presented. The times to failure (tf) are fitted to a combination of the Arrhenius model (ln(tf)∼inverse temperature) and the linear field model (ln(tf)∼drain voltage). The estimated activation energy (Ea) is 2.1eV and the estimated linear field parameter (γ) is 0.03V−1. Reliability parameters estimated from the test structure data are used to predict the FIT rate for a product level FET using linear scaling of the gate width. Further, the effect of a burn-in and a transient voltage under a duty cycle on the FIT rate are modeled. The FIT rate of the product level FET is larger than that of the test structure. The burn-in and transient voltage similarly reduce the reliability. Contour plots are given that allow trade-offs between these factors in order to meet reliability requirements.

Guest Editorial Special Issue on GaN Electronic Devices

Due to the rapid advances taking place in the development and application of GaN electronics, there is an immediate need to take cognizance of the recent technological improvements and bring the potential and opportunities that exist in the area to a wider device community. The primary goal of this special issue is, therefore, to put together works in different aspects, including modeling, design, technology, characterization and applications so that this special issue will not only be of great archival value but also attract new researchers into this area for Digital Object Identifier 10.1109/TED.2013.2278653 further accelerating the application of III-N devices in building reliable, cheaper, and high-performance electronic systems. The papers collected in this special issue have been grouped into six topics. They are: 1) Fabrication and characterization of GaN-based devices. 2) High power GaN HEMTs for power switching applications. 3) High speed GaN HEMTs for RF applications. 4) Reliability and parasitic issues in GaN HEMTs. 5) Simulation-based development of GaN HEMTs devices. 6) GaN-based low noise amplifiers and gate drive circuits.

High-Power Wideband $L$-Band Suboptimum Class-E Power Amplifier

This paper presents a high-power high-efficiency wideband suboptimum Class-E RF power amplifier based on a packaged high-power GaN HEMT. It uses a simple double-reactance compensation and impedance transformation load network that includes device intrinsic capacitance, package parasitics, low-loss microstrip transmission lines, and lumped components. This load network makes the GaN HEMT operate in suboptimum Class-E from 900 to 1500 MHz (50% fractional bandwidth at 1200 MHz). The amplifier can operate both in continuous wave and pulsed modes over its full bandwidth without tuning. It delivers up to 180-W output power with up to 85% drain efficiency and PAE=81%. To the best of the authors' knowledge, the amplifier proposed in this work outperforms commercial grade amplifiers that operate in the same frequency band with similar output power levels. Direct applications for this amplifier include mobile satellite communications transmitters, envelope elimination and restoration digital audio broadcasting transmitters, and power stages for primary and secondary RADAR transmitters.

Temperature-dependent reverse-bias stress of normally-off GaN power FETs

We show results of temperature-dependent reverse-bias step-stressing of normally-off high-power GaN FETs. In the range 250–350K, the stress voltage at which the FETs fail catastrophically does not show a clear temperature dependence, while some correlation is observed with the initial leakage current value. Our results, consistent with other published reports, point to the activation of a deep gate-to-drain leakage path as the responsible for fatal device degradation at large values of the drain–gate reverse bias.

Avalanche Breakdown Design Parameters in GaN

We have studied the avalanche breakdown design parameters of GaN n+/p and p+/n junctions in the voltage range of 1.2 to 12 kV using numerical simulations and analytical calculations. Important analytical models regarding the relationships between breakdown voltages, depletion width, maximum junction electric field and doping concentrations have been extracted which shows very high consistency with the results from numerical simulations. These analytical models can be used as guidelines in the designing of GaN high voltage power devices. The multiplication factors Mn and Mp have also been obtained and the analytical models have been extracted. The results showed that in GaN, n+/p junction is better than p+/n for the main voltage blocking junction due to a sharper avalanche current increase.

Development of Millimeter-wave High Power GaN Amplifier Technology

Development of Millimeter-wave High Power GaN Amplifier Technology

Direct Low‐Temperature Integration of Nanocrystalline Diamond with GaN Substrates for Improved Thermal Management of High‐Power Electronics

AbstractA novel approach for the direct synthetic diamond–GaN integration via deposition of the high‐quality nanocrystalline diamond films directly on GaN substrates at temperatures as low as 450–500 °C is reported. The low deposition temperature allows one to avoid degradation of the GaN quality, which is essential for electronic applications The specially tuned growth conditions resulted in the large crystalline diamond grain size of 100–200 nm without coarsening. Using the transient “hot disk” measurements it is demonstrated that the effective thermal conductivity of the resulting diamond/GaN composite wafers is higher than that of the original GaN substrates at elevated temperatures. The thermal crossover point is reached at ≈95–125 °C depending on the thickness of the deposited films. The developed deposition technique and obtained thermal characterization data can lead to a new method of thermal management of the high power GaN electronic and optoelectronic devices.

Graphene quilts for thermal management of high-power GaN transistors

Self-heating is a severe problem for high-power gallium nitride (GaN) electronic and optoelectronic devices. Various thermal management solutions, for example, flip-chip bonding or composite substrates, have been attempted. However, temperature rise due to dissipated heat still limits applications of the nitride-based technology. Here we show that thermal management of GaN transistors can be substantially improved via introduction of alternative heat-escaping channels implemented with few-layer graphene-an excellent heat conductor. The graphene-graphite quilts were formed on top of AlGaN/GaN transistors on SiC substrates. Using micro-Raman spectroscopy for in situ monitoring we demonstrated that temperature of the hotspots can be lowered by ∼20 °C in transistors operating at ∼13 W mm(-1), which corresponds to an order-of-magnitude increase in the device lifetime. The simulations indicate that graphene quilts perform even better in GaN devices on sapphire substrates. The proposed local heat spreading with materials that preserve their thermal properties at nanometre scale represents a transformative change in thermal management.

AN IMPROVED NONLINEAR CURRENT MODEL FOR GAN HEMT HIGH POWER AMPLIFIER WITH LARGE GATE PERIPHERY

According to the characteristics of high power GaN amplifier, the common current-voltage (I-V) temperature dependence model established by Angelov is improved in this research. Besides embodying the surface temperature distribution, the most important improvement is that it can describe the current decreasing trend under high bias voltage due to trapping related dispersion and self-heating effect. The practical application shows that the prediction accuracy of the large signal equivalent circuit model is improved obviously after introducing the proposed I-V model.

NONLINEAR MODELING OF TRAPPING AND THERMAL EFFECTS ON GaAs AND GaN MESFET/HEMT DEVICES

A novel nonlinear model for MESFET/HEMT devices is presented. The model can be applied to low power (GaAs) and high power (GaN) devices with equal success. The model provides accurate simulation of the static (DC) and dynamic (Pulsed) I-V characteristics of the device over a wide bias and ambient temperature range (from i70 - C to +70 - C) without the need of an additional electro-thermal sub-circuit. This is an important issue in high power GaN HEMT devices where self-heating and current collapse due to traps is a more serious problem. The parameter extraction strategy of the new model is simple to implement. The robustness of the model when performing harmonic balance simulation makes it suitable for RF and microwave designers. Experimental results presented demonstrate the accuracy of the model when simulating both the small-signal and large- signal behavior of the device over a wide range of frequency, bias and ambient temperature operating points. The model described has been implemented in the Advanced Design System (ADS) simulator to validate the proposed approach without convergence problems.

A Ku band internally matched high power GaN HEMT amplifier with over 30% of PAE

We report a high power Ku band internally matched power amplifier (IMPA) with high power added efficiency (PAE) using 0.3 μm AlGaN/GaN high electron mobility transistors (HEMTs) on 6H-SiC substrate. The internal matching circuit is designed to achieve high power output for the developed devices with a gate width of 4 mm. To improve the bandwidth of the amplifier, a T type pre-matching network is used at the input and output circuits, respectively. After optimization by a three-dimensional electromagnetic (3D-EM) simulator, the amplifier demonstrates a maximum output power of 42.5 dBm (17.8 W), PAE of 30% to 36.4% and linear gain of 7 to 9.3 dB over 13.8–14.3 GHz under a 10% duty cycle pulse condition when operated at Vds = 30 V and Vgs = −4 V. At such a power level and PAE, the amplifier exhibits a power density of 4.45 W/mm.

Advanced Manufacturing Methods for Brazing High-Reliability Electronic Packages

Brazing is a critical process for producing reliable adhesion between package metallization and metal components such as heat sinks, seal rings, and connectors. Package performance for signal integrity, mechanical reliability, and thermal management not only relies on improved materials but also on manufacturing methods designed to leverage those improvements. High-reliability packaging for applications in medical, harsh environment or aerospace applications requires a thorough understanding of which fabrication processes to select, as well as fixturing and material preparation to meet increasing demands for low electrical losses at higher frequencies and higher thermal conductivity for high-power GaN and SiC device operation. In the present work, utilization of manufacturing design tools and methods for optimal brazing will be discussed.

High-Power GaN-Based Light-Emitting Diodes Using Thermally Stable and Highly Reflective Nano-Scaled Ni–Ag–Ni–Au Mirror

In this study, we have fabricated the high-power GaN based vertical light-emitting diodes (VLEDs) by exploiting a thermally stable nano-scaled Ni-Ag-Ni-Au mirror. After being treated at 600 °C for 1 min in air ambient, the nano-scaled Ni-Ag-Ni-Au (5/2000/1000/2000 A) mirror shows the specific contact resistance of 6.0 × 10-4 Ω·cm2 and its reflectivity has increased from 89.5% to 93.0%. The increment in the reflectivity is due to the diffusion of Ni contact layer into Ag layer. Moreover, the reflectivity of the mirror has hardly deteriorated even after the wafer was thermally bonded with graphite substrate at 320 °C for 5 min, meaning that the proposed mirror is thermally reliable. The light output power of the nano-scaled VLED (Chip size: 1 × 1 mm2) with thermal treatment at 600 °C for 1 min is enhanced by 8% as compared to one without thermal treatment at an injection current of 350 mA. To our knowledge, our nano-scaled mirror has the highest reflec tivity among other Ag-based multilayered reflectors, and thus it is a promising candidate for high-performance VLED.

Carrier Dynamics Investigation on Passivation Dielectric Constant and RF Performance of Millimeter-Wave Power GaN HEMTs

The effect of the passivation layer dielectric constant and T-gate geometry on the performance of millimeter-wave high-power GaN HEMTs is investigated through a nanoscale carrier dynamics description obtained by full-band cellular Monte Carlo simulation. The effective gate length is found to be increased by fringing capacitances and enhanced by the dielectric constant of the passivation layer in the regions adjacent to the gate for layers thicker than about 5 nm. Detailed simulation results are shown for the carrier energy, velocity, scattering, and electric field profiles along the channel. The output impedance under small- and large-signal operations is also discussed. Our results indicate that the effect of the passivation layer dielectric constant changes the nanoscale carrier dynamics and can strongly affect the radio-frequency performance of deep submicrometer devices.

(Invited) High Voltage Normally-Off Transistors and Efficient Schottky Diodes based on GaN Technology

High voltage GaN based power switching transistors in normally-off technology and efficient GaN Schottky di-odes are indispensable for a steady improvement of effi-ciency in power converters and for cutting down volume and weight of these systems. To obtain ultimate device performance, novel concepts in epitaxial design and growth techniques as well as in processing and packaging technology are required. At FBH, normally-off GaN based power transistors and Schottky diodes have been and are being developed. These efforts cover the full val-ue added chain from epitaxial growth of GaN/AlGaN de-vice structures on 3" n-type SiC substrates, device proc-essing, characterization and interfacing to novel packag-ing techniques. The paper will summarize the most im-portant achievements towards high power GaN devices at FBH and will show up important dependencies towards further improved GaN power devices.

EXTRACTION OF GATE CAPACITANCE OF HIGH-FREQUENCY AND HIGH-POWER GaN HEMTs BY MEANS OF CELLULAR MONTE CARLO SIMULATIONS

A high-frequency a high-power GaN HEMT was analyzed using our full band Cellular Monte Carlo (CMC) simulator, in order to extract small signal parameters and figures of merit, and to correlate them to carrier dynamics and distribution inside the device. A complete RF and DC characterization of the device was performed using experimental data to calibrate the few adjustable parameters of the simulator. Then, gate-related capacitances, such as Cg, Cgd, and Cgs, were directly and indirectly extracted combining small-signal analysis and DC characterization.

GaN High Power Electronics

not Available.

Sub-1-dB Noise Figure Performance of High-Power Field-Plated GaN HEMTs

In this letter, we report the state-of-the-art micro wave noise performance of discrete 0.15-μm-gate-length field plated (FP) GaN HEMTs. The FP GaN HEMTs yielded a peak fτ/f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 60 GHz/150 GHz at Vds = 10 V. An f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 230 GHz was obtained at Vds = 20 V. At 2.5 V, the source-drain bias and dc power dissipation of 200 mW/mm, a minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) of 0.89 dB, and an associated gain (AG) of 11 dB were measured at 10 GHz. At 20 GHz the NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> and AG were 1.9 and 6.2 dB, respectively. The sub-1-dB microwave noise performance at 10 GHz is the best ever reported for FP high-power GaN HEMTs, which can be attributed to their lateral scaling and deep-submicrometer gate lengths.

ChemInform Abstract: Recent Progress on ZnO‐Based Metal‐Semiconductor Field‐Effect Transistors and Their Application in Transparent Integrated Circuits

AbstractReview: 52 refs.

Thermal and Mechanical Characterization of High Power GaN Packages

The typical package available for high power GaN application has the devices directly attached onto a metal flange, which could contribute significantly to the overall thermal resistance. This paper discusses an alternative approach to packaging both single and multiple devices through a heat spreader, which could potentially improve thermal performance and bring significant benefits to assembly in yields and cost. However, the heat spreader could also introduce significant CTE mis-match and potential concerns in reliability. Nonlinear 3D finite element analysis (FEA) was conducted to characterize the thermal performance and evaluate mechanical/reliability concerns. Thermal modeling considered single and multiple die applications, and the results show13–15% thermal improvement with the copper heat spreader. Mechanical analysis focused on the thermal loads of the die attach and solder reflow processes. It reveals that the die attach process is more critical as shown in the higher stress due to higher thermal load, but stress/strain levels appear to be acceptable. Thus, this alternative approach could be a viable solution.