High Pin Count Research Articles

Optimization of high pin count cavity-up enhanced plastic ball grid array (EPBGA) packages for robust design

Three-dimensional (3-D) nonlinear finite element models of epoxy encapsulated enhanced plastic ball grid array (EPBGA) packages with and without an aluminum lid have been developed using ANSYS finite element simulation code. The model has been used to optimize the packages for robust design and to determine design rules to keep package warpage within acceptable limits. An L/sub 18/ Taguchi matrix has been developed to investigate the effect of die attach and encapsulant properties along with the substrate, encapsulant, die attach, and internal copper plane thicknesses on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling from 165/spl deg/C to -65/spl deg/C. This condition is approximated by cooling the package mounted on a multilayer printed circuit board (PCB) from 165/spl deg/C to -65/spl deg/C. For coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 20/spl deg/C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, encapsulant as well as die attach material should have low Young's modulus and low coefficient of thermal expansion. Furthermore, it is found that the substrate and the die attach epoxy thicknesses should be increased beyond the current design. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of the possible first solder ball failure.

Design of a Low‐cost Wire Bond Tape Ball Grid Array Package

Tape ball grid array (TBGA) packages offer many of the advantages of plastic BGAs, namely excellent durability, improved board space utilisation and ease of surface mount assembly along with the associated yield improvements. TBGA packages go a step further, however, and offer the added benefits of improved signal integrity, better heat dissipation, and extendability to higher pin counts. This paper outlines the design and material selection process to produce a low‐cost TBGA which allows the wire bonding of a die. This type of package offers an attractive solution for applications requiring mid to high I/O capability and good electrical and thermal properties. Preliminary results have demonstrated the feasibility of wire bonding to this package at temperatures up to 200°C.

Thermal performance comparison of high pin count cavity-up enhanced plastic ball grid array (EPBGA) packages

Three-dimensional finite element models of cavity-up enhanced plastic ball grid array (EPBGA) packages have been developed using ANSYS finite element simulation code. The models have been used for thermal characterization of different designs of high pin count EPBGA packages under different air flow conditions with and without an external heat sink. In addition to the design evaluations, the simulations have been repeated to quantify the effect of populated and unpopulated boards on the thermal performance of each EPBGA package with and without a heat sink. For the unpopulated board case, a single package has been modeled on a 10 cm/spl times/10 cm/spl times/0.16 cm (4"/spl times/4"/spl times/0.062") multilayer printed circuit board (PCB). For the populated board, the size has been reduced to the size of the package footprint, and no heat transfer is permitted along the board periphery. Further parametric studies have been performed to predict the thermal performance of EPBGA packages as a function of solder ball counts in the inner solder ball matrix (underneath the cavity). In conjunction, the optimum number of solder balls in the inner matrix has been determined for better heat dissipation through the package to the board via the thermal balls. In addition to the solder ball counts, the importance of the package internal vias connected to the solder balls in the inner matrix is quantified. The predicted results have been plotted as functions of the junction-to-ambient resistance (/spl theta//sub JA/) and the air speed for different package designs. It is also found that the junction-to-case resistance (/spl theta//sub JC/) significantly drops when the solder bails are placed in the inner matrix underneath the die. The thermal performance would not be significantly improved when more than 48 solder balls are placed underneath the die region.

Carrier and socket technology for high pin count WEP packages : JOSEPH W. FOERSTEL. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, 18(1), 136 (March 1995)

Carrier and socket technology for high pin count WEP packages : JOSEPH W. FOERSTEL. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part A, 18(1), 136 (March 1995)

エレクトロニクスにおけるマイクロ接合技術の進展と課題 ＴＡＢテープにおける狭ピッチ・多リード化

エレクトロニクスにおけるマイクロ接合技術の進展と課題 ＴＡＢテープにおける狭ピッチ・多リード化

ＬＳＩリードフレーム材料の接続に関する研究（第１報）リードフレームはんだ付部の引き剥がし強度特性

Representative electric parts, LSI packages are turning to more fine pitch and more high pin count based on the demands of package size reduction which is coming from needs of smaller electric components. This reserch work has originated from high density LSI package surface mounting, including microjoining of leadframe on printed circuit board. In surface mounting of electric parts, solder past mass reflow line is applied to microjoining of fine pitch leadframe even less 0.5 mm pitch package outer lead on account of easy process controll and massproduction. But leadframe materials tend to smaller lead width and thinner by fine pitch photochemical etching technology propagation. This reserch work focused on reliability of fine pitch leadframe made with copper metal and Fe-42 mass% metal alloy surface mounted with solder past through long run aging.The result of this study have shown that fine pitch surface mount with solder paste (min. 0.3 mm pitch) is capable. But after high temperature aging (150°C×1000 h in air), Pb-60Sn eutectic microstructure of solder at leadframe microjoined is segregated to Pb rich and Sn rich large grain. And copper leasds become thin by high temperature reaction with solder. It was determined that copper was damaged in high temperature circumstance.

Field-based analysis of a high pincount board connector

Field-based analysis of a high pincount board connector

C-4/CBGA comparison with other MLC single chip package alternatives

Future applications, will require higher I/O counts, more densification, lower cost, and greater performance. This paper demonstrates why area-array based chip-to-substrate and substrate-to-card interconnections are strategic, particularly solder bump flip chips (SBFC or C-4) and ceramic ball or column grid arrays (CBGA/CCGA), respectively. That is, SBFC are capable of high pin counts coupled with high yields, performance, and reliability. Moreover, recently introduced CBGA/CCGA interconnections provide substantial benefits over standard pin grid array (PGA) packages. Also, CBGA/CCGA packages possess the highest density achievable at the card level when utilized in conjunction with SBFC-mounted die.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Present and future directions for multichip module technologies

Multichip modules (MCM's) have been actively developed in recent years. They are expected to provide high-performance systems by packing bare chips at a high density. In particular, a thin-film interconnect substrate that can accommodate higher wiring capacity in a few layers is a new option for coping with high pin count and fine pad pitch VLSI's. MCM's require various kinds of technologies including the fabrication processes of interconnect substrates, chip connection methods, electrical design, thermal management, known good die (KGD), and so on. The state of the art of MCM technologies is reviewed and future directions are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Carrier and socket technology for high pin count QFP packages

The carrier and socket technology for high pin count Quad Flat Pack (QFP) packages is a set of three components that can be used in various combinations, that allow for easier manipulation of fine pitch, (fine pitch defined as packages having a lead tip to lead tip spacing of 0.65 millimeters or less), QFP between various shipping, test, programming, and prototype environments. The three components are the small outline carrier, surface mountable development socket, and through hole mountable programming socket. The carrier is designed to protect the leads of the QFP from deformation, while allowing the leads to make electrical connection with the contacts of the two different sockets. The development socket is surface mountable with a footprint that is identical to the naked QFP housed within the carrier. The programming socket is a through hole mountable, clam-shell socket, which accepts the same carrier as the development socket. The carrier and socket technology was developed primarily to assist in the development and prototyping of re-configurable QFP devices. Specifically, those QFP devices that need to be placed in a different electrical environment to be re-configured, than the electrical environment the device will be in, once it has been configured to the users satisfaction. >

The boundary scan

Miniaturization trends in integrated circuit (IC) technology have caused many testing problems. As bigger packaged ICs with higher pin counts are more densely packed onto a printed circuit board (PCB), accessing an IC's pins is harder. No longer are the pins mechanically accessible to probes or a bed-of-nails fixture. Therefore, determining which IC or interconnect is faulty is difficult or impossible. Because each IC's input pins cannot be controlled, and each IC's output pins cannot be observed. The boundary scan method was developed with the goal of improving this controllability and observability problem. A shift-register is included next to each IC pin so that input and output values can be serially shifted in and out. This reduces the need to use probes to control and observe. Also, the output of each IC's scan register can be connected with the input of another IC's scan register. This effectively creates one big scan chain per PCB, further reducing points that must be mechanically probed. The inclusion of a scan-register on each IC allows: 1) the observation of each IC during normal operation; 2) the test of interconnects between ICs, and 3) the isolation of the IC from others so it can test itself. The IEEE Standard 1149.1 Test Access-Port and Boundary Scan defines the test logic for implementing a boundary scan test architecture. Example circuits were designed in CMOS. A boundary scan cell is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

System design optimization for MCM-D/flip-chip

Many performance/cost advantages can be gained if a chip-set is optimally redesigned to take advantage of the high wire density, fast interconnect delays, and high pin-counts available in MCM-D/flip-chip technology. Examples are given showing for what conditions the cost of the system can be reduced through chip partitioning and how the performance/cost of a computer core can be increased. >

A micromachined array probe card-characterization

An array probe card fabricated on a silicon wafer for high performance and high pin count applications is characterized. The probe card is capable of providing a very large number of probe tips (>1000) that offer a contact resistance of less than 2 /spl Omega/. A novel approach to replacing the mechanical scrubbing motion with an electrical breakdown process is presented. The probe card is capable of operating at elevated temperatures for extended periods of time, offers alternative probe tip configurations, and is capable of probing a variety of pad metals. Controlled impedance (50 /spl Omega/) striplines that run all the way to the probe tips offer a delay time of 68 ps/cm, 3 GHz bandwidth, and far-end cross-talk of -49 dB/cm at a pitch of 32 /spl mu/m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Excimer Laser Applications in Integrated Circuit Packaging

ABSTRACTExcimer laser ablation is applied in the deflashing and demarking of IC packages. It is found that mold flash filled in the interface holes of IC leadframe can be removed completely by the laser deflashing in a short period of time. With appropriate selection of laser parameters, deflashing quality and efficiency can be greatly improved. The laser deflashing is more efficient for higher pin count packages. It is a superior alternative in future applications. In laser demarking, ink marks on package surfaces can also be removed completely in a short time. The surface after the processing has good conditions for remarking. The package remarking shows good permanency. The lifetime for good marking is much longer for IC packages after the laser demarking than those after hydrogen flame-off. Laser processing can be used to replace hydrogen flame-off in the ink printing of IC packages for high efficiency and safety.

Thin QFP—the next generation high pincount surface mount challenge : Robbyn Culver, Richard Groover, Ahmad Hamzehoost and Chin C. Huang. Microelectronics Journal, 24(3), 181 (1993)

Thin QFP—the next generation high pincount surface mount challenge : Robbyn Culver, Richard Groover, Ahmad Hamzehoost and Chin C. Huang. Microelectronics Journal, 24(3), 181 (1993)

Reliability of area array pressure contacts on the DTAB package

Pressure contacts using noble metals have been in use for a long time. The contact metallurgy, the design, and the reliability are well understood and proven in a variety of applications, including relays, connectors, sockets, and other separable contacts. Pressure contacts in VLSI package applications are rather new. The large number of contacts at fine pitch and operation at high frequency and power present problems in design, materials, and reliability not encountered in other applications. Demountable TAB (DTAB) is a VLSI package, developed and qualified for high performance (/spl Gt/100 MHz), high pincount (>400) ASIC's with higher power dissipation (/spl sim/40 W). It is a TAB-based package that utilizes area array, gold-to-gold pressure contacts to connect the tape to the printed circuit board, instead of the conventional reflowed solder joints. Extensive reliability testing has been used to optimize the design as well as to qualify the package for product applications. The formal tests have been extended beyond the industry standards to include system level tests, designed to stress the pressure contact under conditions not expected from other equivalent packages. Testing during the development phase revealed failure mechanisms that relate to the mechanical design of the spring system that maintains the force on the contacts; materials relaxation over extended periods of time under severe environmental conditions; and creep deformation of the printed circuit board under uneven distribution of clamping forces. Testing has also revealed that this package produces very high reliability sealed contacts, although thin gold of 5 /spl mu/in thickness is used instead of the 50-/spl mu/in thickness conventionally required by other applications. The test and testing methodology are discussed; the results and the failure modes and analysis are presented. The design changes and materials used to eliminate the failures are described. >

High-speed, low-switching noise CMOS memory data output buffer

This paper describes a data output buffer for highspeed CMOS integrated memories with a high data output pin count. The buffer minimizes the switching noise induced on supply lines while achieving very fast output transitions by combining output presetting techniques together with adequate driving of the output pull-up and pull-down transistors. Tristate operation and zero static power consumption are also provided. The buffer was integrated in a 16-Mb EPROM device. It occupies 0.06 mm/sup 2/ and ensures a better than 15 ns output transition time with a load capacitor of 100 pF. >

Surface mounting of very fine pitch components: a new challenge

Based on their experience in developing and using 16 and 12.5 mils peripheral pitch custom compact single chip packages, the authors analyze the evolution and today's limits of package and board technologies and assembly techniques, with emphasis on manufacturability. The authors present their manufacturing approach and quality and reliability results when using 16 and 12.5 mils peripheral ceramic leaded packages. A detailed analysis of packaging processes and limitations is performed for high pin count ceramic and plastic packages. Competitive packaging methods, pin grid arrays, land grid arrays, and tape automated bonding are compared, and trends for the future are analyzed. >

A new de-embedding technique for on-board structures applied to the bandwidth measurement of packages

A de-embedding technique for on board structures or devices under tests (DUTs) is presented. The key feature of the method is the comparison between the S-parameter data for the embedded DUT and the data for a judiciously chosen reference situation. The technique also uses the time-domain option of modern network analyzers. The approach is illustrated by detailed bandwidth measurements for a high pin count package.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Thin QFP — the next generation high pincount surface mount challenge

Surface mount technology has revolutionized almost all aspects of end user product development. The commercial market in Japan has used low pin count surface mount packages for many years. Europe and the United States are rapidly expanding their own surface mount manufacturing expertise.