High Pin Count Research Articles

Thermal‐mechanical Processing and Repairability Observations for FR‐4, Cyanate Ester and Cyanate Ester/Epoxy Blend PCB Substrates

Thermal cycling tests and failure modelling were conducted on FR‐4 and cyanate ester printed circuit board (PCB) substrate materials to evaluate reliability limits tor solder and repair processes, particularly for high pin count, through‐ hole devices. The boards used were double‐sided, 0.125 in. thick with 0.029 in. diameter plated‐through holes (PTHs). Thermal cycling was accomplished using hot oil immersion at 240°C and 260°C followed by forced room‐temperature air. The average number of thermal cycles‐to‐failure was 10 for FR‐4, 20 for cyanate ester epoxy blend, and 50 for cyanate ester. Weibull statistics were used to predict failure rates for various pin count devices. Failure analysis was used to identify the mechanism of failure, and modelling was used to predict cycles‐to‐failure based on typical material properties. The primary failure mechanism was corner cracking in FR‐4 and a combination of corner cracking and barrel cracking in the cyanate ester materials. The modelling used a modified pad tilt geometry combined with Coffin‐Manson low cycle fatigue theory, which resulted in predictions of the same order as those for the cycling tests. Key material properties and process parameters were identified that controlled the failure response of the plated‐through hole and board substrate combinations.

特集 高密度実装とプリント配線板 フルアディティブ基板を用いたＴＣＰおよび多ピンＱＦＰの実装

特集 高密度実装とプリント配線板 フルアディティブ基板を用いたＴＣＰおよび多ピンＱＦＰの実装

An ATM switch hardware technologies using multichip packaging

An asynchronous transfer mode (ATM) switching system constructed of copper-polyimide multilayer multichip modules (MCMs) is described. High throughput ATM switching systems require high-speed interconnections and high-density packaging to reduce the interconnection lengths. An ATM prototype switching system which consists of two ATM switch MCMs was developed. The ATM switch MCM contains 24 LSIs and a multilayer substrate with polyimide dielectric and a fine pattern copper conductor. A fine pitch flexible lead 680-way connector was developed to achieve a high-speed interconnection between the MCM and printed circuit board. Tap automated bonding (TAB) was used to allow pretesting of the LSI devices and to mount high pin count LSI devices onto the MCM. The system performed 16*16 ATM cell switching at 150 Mb/s. Furthermore, it transmitted NRZ signals of up to 810 Mb/s between MCMs via fine-pitch flexible lead connectors and a 40-cm line in the printed circuit board.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Stress Analysis and Thermal Characterization of a High Pin Count PQFP

A three-dimensional finite element model of a high pin count plastic-quad-flat-pack (PQFP) has been developed by using ANSYS™ finite element simulation code [1]. The model has been used for both thermo-mechanical stress analysis during temperature cycling and thermal characterization of the package under forced air cooling. Parametric studies have been performed on two different molding compounds with and without a drop-in heat spreader. In addition, the model has been simplified by substituting the leadframe and molding compound with a single homogeneous material, reflecting both molding compound and the leadframe thermo-physical properties. Results from the molding compound parametric studies indicate a lower package stress if the molding compound with low thermal expansion coefficient is used. Comparisons of principal and von Mises stresses show that the simplified model, overall, underpredicts the stresses. Although both the simplified and detailed models predict almost the same value for junction-to-case resistance (θJC), calculated values are significantly lower than the measured θJC. In contrast to θJC, the predicted junction-to-ambient resistances (θJA) are in good agreement with the measured data.

Reliability evaluation of high pin count hermetic ceramic IC packages for space applications

Reliability evaluation of high pin count hermetic ceramic IC packages for space applications

Mechanical Deformation of Leadframe Assemblies in Plastic Packages During Molding

We evaluate the maximum stresses and deflections in electric leads subjected to flow induced forces during transfer molding of plastic packages. It is found that lead deflection is proportional to the fifth power of the lead length and the inverse third power of lead thickness. These dependencies explain why it is more difficult to mold high pin count packages which have significantly longer and thinner leads to accommodate the higher interconnection density. In addition we find that the maximum value of the elastic lead deformation is about 0.9 mm (35 mils) for large state-of-the-art packages; exceeding this value causes permanent (plastic) lead distortion that compromises the symmetry of the package. We find also that minimizing the difference in flow front locations through careful gate design, and lowering the velocity over the leads by using balanced mold filling can make a significant difference in lead deformation. The results obtained are useful in establishing the appropriate geometry of the leads, as well as in choosing the materials and process parameters, so that excessive stresses and lead deflections can be avoided.

Design Factors With Realistic I/O Distributions

This paper explores some design factors, including wireability, of packages in which the number of I/O per module to be interconnected varies widely. This is of interest because it is common for memory card designs and for work station and personal computer printed circuit designs. Memory cards often have a few relatively high pin count control logic modules supporting many low pin count array modules. Work station and personal computer cards often use low density “glue” logic modules with a few microprocessor modules and their high function supports. Printed circuit cost and performance factors are examined by example. Differences between area array and perimeter escape components and leverage possibilities of multi-chip modules are examined. A background tutorial on wireability analysis is given. The algorithm used was developed by Wadie Mikhail several years ago. Analyses are based on the length of wire paths available in a given design, the length of wire needed and the utilizations of the available paths. Utilization guidelines are suggested. Alternative wireability algorithms are identified and briefly discussed. Although the examples are given for cases of modules on cards, the methodologies and general conclusions are valid at other packaging levels; for example, for chips on multi-chip modules.

High Pin-Count Packaging: PLCC—The way to go

Chip designers are putting more and more components on a single chip. The more complex the function of the chip, greater is the demand on signal and power lines leading to a high pin-count chip. On the other hand, system designers are preferring surface mount technology which leads to cost savings in the printed circuit board. Caught in this cleft is the semiconductor packaging engineer, who has to design new innovative packages which are not only of high pin-count but also amenable to new assembly technique of surface mounting. In this paper new packaging techniques such as PGAs, PLCCs, LCCs, LLCCs, PQFPs and TAB are surveyed.PLCC is the most cost effective high pin-count packaging technology. Details of PLCC packaging process along with relevant equipment issues are also presented in this paper.Finally, some guidelines for process optimization and good practices are enumerated.

New developed of thin plastic package with high terminal counts

A small and thin quad flat package (QFP)-type plastic package for large-scale integrated (LSI) logic devices with high pin counts has been developed. The size of the package with 252 input and output pins is 17.3 mm by 17.3 mm, and the thickness is 1.52 mm. The pitch and the width of the leads are 0.25 and 0.1 mm, respectively. The main technologies for assembly of the package are tape automated bonding (TAB) interconnection technology, which has been developed for bonding of high-terminal-count LSIs, and the molding technology, which has also been developed for very small and thin plastic packages. The reliability of the package and the outer lead bonding of the package were evaluated, and it was confirmed that both the package and the bonding have no problem in the pressure cooker test (PCT), the temperature cycle test, and the high-temperature-storage test. >

High density packaging technology ultra thin package &amp; new tab package

As electronic devices become more highly integrated, the demand for small, high pin count packages has been increasing. We have developed two new types of IC packages in response to this demand. One is an ultra thin small outline package (TSOP) which has been reduced in size from the standard SOP and the other, which uses Tape Automated Bonding (TAB) technology, is a super thin, high pin count TAB in cap (T.I.C.) package. In this paper, we present these packages and their features along with the technologies used to improve package reliability and TAB. Thin packages are vulnerable to high humidity exposure, especially after heat shock.1 The following items were therefore investigated in order to improve humidity resistance: (1) The molding compound thermal stress, (2) Water absorption into the molding compound and its effect on package cracking during solder dipping, (3) Chip attach pad area and its affect on package cracking, (4) Adhesion between molding resin and chip attach pad and its affect on humidity resistance. With the improvements made as a result of these investigations, the reliability of the new thin packages is similar to that of the standard thicker plastic packages.

The Optimal Choice of High Pin Count ASIC Packages

The choice of high pin count ASIC packages has a major impact on the total cost and performance of the whole packaging system. Six different types of ASIC packages have been compared with respect to production aspects, availability, reliability, thermal and electrical properties and cost. Recommendations for the proper choice of packages for different types of applications are given. All packages have been directly assembled to PWBs in order to study problems with handling, solder process, testing and repairability. Some of the assembled packages have been temperature cycled in order to test the solder joint reliability. The pin grid array packages are the most frequently used high pin count packages today. However, they are expensive and through‐hole mounting reduces the routing capability of the board. Pad area array packages are a hermetic alternative with a lower price for the package as well as very good thermal and electrical properties, but they need to be mounted on expensive PWBs. Another surface mountable package which is hermetic is the ceramic leaded chip carrier with fine lead pitch. This package is even more expensive than the pin grid array package and is difficult to handle. In the future, non‐hermetic alternatives will probably predominate. Plastic quad flat pack and TapePak can be used below 160–180 leads, while direct assembled TAB would be the best alternative for very high pin counts. Before one can use non‐hermetic packages in telecom products, a large qualification programme must be performed to evaluate the long‐term reliability.

Wafer-level testing with a membrane probe

The authors describe a proprietary membrane probe card that addresses the needs of testing VLSI devices at the wafer level. The membrane probe allows the testing of devices with a high pin count at operating speed, while allowing a complete package test at the wafer level. The concepts and structure of the probe are examined, and its performance is demonstrated by time-domain and frequency-domain measurements of the typical electrical characteristics of a VLSI digital probe that accesses 272 pads at a pitch of 110 mu m. Applications to a bipolar ECL (emitter-coupled logic) flash A/D (analog-to-digital) converter, a bipolar ECL D/A converter, an application-specific CMOS IC, an NMOS VLSI central processing unit, and area-array solder bumps are presented. >

Design, manufacture, and assembly of high pin count plastic pin grid array packages : Martin F. Blackshaw and Francis J. Dance. Solid St. Technol., 141 (August 1986)

Design, manufacture, and assembly of high pin count plastic pin grid array packages : Martin F. Blackshaw and Francis J. Dance. Solid St. Technol., 141 (August 1986)

Testing logic arrays

Designing for testability is the aim of every manufacturer of semi-custom devices. As these devices become more complex with unusually high pin counts, manufacturers must be able to test them whilst maintaining the level of quality and efficiency. This paper looks at Level Sensitive Scan Design, Scan testing and describes briefly the LDSI development system which has simplified the testing of semi-custom circuits developed by LSI.