MicroSMD-a wafer level chip scale package

Abstract

This paper outlines National Semiconductor's concept of wafer level chip scale package-also known as microSMD. This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability.