Thermal performance comparison of high pin count cavity-up enhanced plastic ball grid array (EPBGA) packages

Abstract

Three-dimensional finite element models of cavity-up enhanced plastic ball grid array (EPBGA) packages have been developed using ANSYS finite element simulation code. The models have been used for thermal characterization of different designs of high pin count EPBGA packages under different air flow conditions with and without an external heat sink. In addition to the design evaluations, the simulations have been repeated to quantify the effect of populated and unpopulated boards on the thermal performance of each EPBGA package with and without a heat sink. For the unpopulated board case, a single package has been modeled on a 10 cm/spl times/10 cm/spl times/0.16 cm (4"/spl times/4"/spl times/0.062") multilayer printed circuit board (PCB). For the populated board, the size has been reduced to the size of the package footprint, and no heat transfer is permitted along the board periphery. Further parametric studies have been performed to predict the thermal performance of EPBGA packages as a function of solder ball counts in the inner solder ball matrix (underneath the cavity). In conjunction, the optimum number of solder balls in the inner matrix has been determined for better heat dissipation through the package to the board via the thermal balls. In addition to the solder ball counts, the importance of the package internal vias connected to the solder balls in the inner matrix is quantified. The predicted results have been plotted as functions of the junction-to-ambient resistance (/spl theta//sub JA/) and the air speed for different package designs. It is also found that the junction-to-case resistance (/spl theta//sub JC/) significantly drops when the solder bails are placed in the inner matrix underneath the die. The thermal performance would not be significantly improved when more than 48 solder balls are placed underneath the die region.