Abstract
Based on their experience in developing and using 16 and 12.5 mils peripheral pitch custom compact single chip packages, the authors analyze the evolution and today's limits of package and board technologies and assembly techniques, with emphasis on manufacturability. The authors present their manufacturing approach and quality and reliability results when using 16 and 12.5 mils peripheral ceramic leaded packages. A detailed analysis of packaging processes and limitations is performed for high pin count ceramic and plastic packages. Competitive packaging methods, pin grid arrays, land grid arrays, and tape automated bonding are compared, and trends for the future are analyzed. >
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