High-performance VLSI Research Articles

Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits

A single path delay fault of a circuit is reduced to a fault in the literal in the equivalent normal form (ENF) that corresponds to the path that acts during the path delay. Based on the analysis of the ENF circuit, we have found properties of pairs of robust and nonrobust test vectors. We show possibilities to reduce the length of the test for path delay faults.

Effect of electric field on metallic SWCNT interconnects for nanoscale technologies

The influence of an electric field on metallic single walled carbon nanotube (SWCNT) interconnects is studied. A voltage-dependent equivalent circuit model is presented for the impedance parameters of single-wall carbon nanotubes that capture various electron-phonon scattering mechanisms as a function of the electric field. To estimate the performance of SWCNT bundle interconnects, signal delay and power dissipation are calculated based on the field dependent model that results in an improvement in the delay and power estimation accuracy compared to the field-independent model. We find that the power delay product of a SWCNT bundle increases with the increase in electric field but decreases with technology scaling showing that at a low electric field, the SWCNT bundle is a potential reliable alternative interconnect for future high performance VLSI industry at scaled technologies.

High Performance VLSI Architecture for Three-Step Search Algorithm

Motion estimation is the most computationally intensive part of any video coding standard. The three-step search algorithm is a popular fast search technique to reduce complexity in motion estimation. In this paper, we propose a novel architecture for the three-step search technique that simplifies memory addressing and reduces hardware complexity. The proposed architecture minimizes the area while maintaining the speed requirements for real-time video processing. Implemented in Verilog HDL on Virtex-5 technology and synthesized using Xilinx ISE Design Suite 14.1, the critical path in the hardware is 6.536 ns and the equivalent area is calculated to be 2.3 K gate equivalent.

Complexity optimization and high-throughput low-latency hardware implementation of a multi-electrode spike-sorting algorithm.

Reliable real-time low-latency spike sorting with large data throughput is essential for studies of neural network dynamics and for brain-machine interfaces (BMIs), in which the stimulation of neural networks is based on the networks' most recent activity. However, the majority of existing multi-electrode spike-sorting algorithms are unsuited for processing high quantities of simultaneously recorded data. Recording from large neuronal networks using large high-density electrode sets (thousands of electrodes) imposes high demands on the data-processing hardware regarding computational complexity and data transmission bandwidth; this, in turn, entails demanding requirements in terms of chip area, memory resources and processing latency. This paper presents computational complexity optimization techniques, which facilitate the use of spike-sorting algorithms in large multi-electrode-based recording systems. The techniques are then applied to a previously published algorithm, on its own, unsuited for large electrode set recordings. Further, a real-time low-latency high-performance VLSI hardware architecture of the modified algorithm is presented, featuring a folded structure capable of processing the activity of hundreds of neurons simultaneously. The hardware is reconfigurable “on-the-fly” and adaptable to the nonstationarities of neuronal recordings. By transmitting exclusively spike time stamps and/or spike waveforms, its real-time processing offers the possibility of data bandwidth and data storage reduction.

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.

High-performance VLSI architectures for turbo decoders with QPP interleaver

This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.

Timing Optimization and Noise Tolerance Dynamic CMOS Logic Design

CMOS logic circuits are used in high performance VLSI chips in order to achieve very high system performance. These circuits requireless number of transistors as compare to CMOS logic circuits. But they suffer from limitations such as noise tolerance, charge leakage, and power consumption. This noise induce in circuits will affect the performance of dynamic circuits. The our work base on noise of MOSFET in contrast to the conventional method which measures drain current noise of MOSFET and divides it by MOSFET transconductance. Therefore, the need for accurate measurement of I-V characteristics of the MOSFET is eliminated, leading to the better accuracy of the measured noise. To design a noise tolerable circuit using dynamic CMOS logic, a new noise tolerant technique is proposed here and then with the help of software we perform parametric analysis to improve the parameters such as noise margin, worst case delay, delayuncertainty, delay sensitivity from their initial performances. By studying those effects we try to put such parameters which help us to make a noise tolerable circuit. Index terms Dynamic Logic Structure, Charge sharing, Keeper logic

Development of low power Dynamic threshold PCS System

Real-time reception of sensor signals is one of the most significant operations in analog signal processing. Driven by low-power and low-voltage requirements for integrated mixed signal portable applications, this paper propose a novel low power Dynamic Threshold Photo Catalytic Sensor (DTMOS)system to work efficiently below lower bound of power supply independent of substrate bias effect. Another important feature of DTMOS is that the fabrication of circuits based on DTPCS is less complex and more economical. The SPICE simulations were performed with 120 nm technology parameters and results verify the performance of the circuit. The proposed system has high linearity and simple structure hence it is suitable for high-performance and low-power analog VLSI applications. The main reason of employing a readout circuit to PCS circuitry, is the fact that the fluctuation of O2 influences the threshold voltage, which is internal parameter of the FET and can manifest itself as a voltage signal at output but as a function of the trans-conductance gain. The trans- conductance is a passive parameter and in order to derive voltage or current signal from its fluctuations the sensor has to be attached to readout circuit. This circuit provides high sensitivity to the changes in percentage of O2 in the solution.

Low Power and High Performance VLSI Interconnects By Schmitt Trigger Technique In Nanoscale Regime

Low Power and High Performance VLSI Interconnects By Schmitt Trigger Technique In Nanoscale Regime

DFAL: Diode-Free Adiabatic Logic Circuits

The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.

Characteristics of double-gate SOI CMOS nanotransistors for promising technologies with a low power consumption level

A procedure, allowing one to optimize topological and electrophysical parameters of double gate SOI nanotransistors with a thin unalloyed working area, with underlap gate and drain/source regions with regard to the physical restrictions and process requirements, without recourse to the 2D-simulation, is considered. Based on the numerical simulation results, the selection criteria of the key topological parameters of transistors for implementing the requirements in accordance with the International Technology Roadmap for Semiconductor 2010 Edition program for promising applications with a low power consumption level are discussed. The complex analysis of the VACs of transistors and gate characteristics, such as a time switching delay, as well as active and static power, shows that prototypes of the considered units are applicable for implementing high-performance VLSI projects.

VLSI IMPLEMENTATION OF FIR FILTER USING COMPUTATIONAL SHARING MULTIPLIER BASED ON HIGH SPEED CARRY SELECT ADDER

Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI Digital Signal Processing (DSP) systems. One of the most widely used operations in DSP is Finite-Impulse Response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital Finite Impulse Response (FIR) filter for high-performance applications. The architecture is based on a computational sharing multiplier which specifically doing add and shift operation and also targets computation re-use in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA) can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 8-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. In which the number of transistor, power (mW) and clock cycle (ns) of the filter using array multiplier are 6000, 3.732 and 9 respectively. The FIR filter using CSHM in which the number of transistor, power (mW) and clock cycle (ns) are 23500, 2.627 and 4.5 respectively. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method. The CSHM scheme and circuit-level techniques helped to achieve high-performance FIR filtering operation.

An Efficient VLSI Architecture for FIR Filter using Computation Sharing Multiplier

Recent advances in mobile computing and multimedia applications demand high-performance and low-power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite-impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high-performance applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically doing add and shift operation and also targets computation reuse in vector-scalar products. CSHM multiplier can be implemented by Carry Select Adder which is a high speed adder. A Carry-Select Adder (CSA) can be implemented by using single ripple carry adder and add-one circuits using the fast all-one finding circuit and low-delay multiplexers to reduce the area and accelerate the speed of CSA. An 4-tap programmable FIR filter was implemented in tanner EDA tool using CMOS 180nm technology based on the proposed CSHM technique. By adopting the proposed method for the design of FIR filter, the delay is reduced to about 43.2% in comparison with the existing method.

High performance VLSI architecture for block based visible image watermarking

In this article, a novel block-based visible image watermark VLSI architecture design and its hardware implementation in field programmable gate array (FPGA) is proposed. In this watermarking process, 1D-DCT is introduced to facilitate hardware implementation. Mathematical model is developed to reduce the computational complexity for the calculation of embedding and scaling factors, which are used to make the resultant image of best quality with uniform watermark visibility. The proposed architecture has a 12–stage pipeline. Parallelism techniques are employed in block level in order to achieve high performance. A single 8-point fast 1D-DCT is used to calculate the DCT coefficient values of the host image and the watermark image to minimize the resource utilization and power consumption. The hardware implementation of this algorithm leads to numerous advantages including reduced power, area and higher pipeline throughput. The performance of the architecture is studied by implementing Xilinx Virtex V technology based FPGA with DSP 48E. Throughput achieved based on this VLSI architecture is 5.21 Gbits/s with a total resource utilization of 4058BELs.

Design and implementation of reconfigurable FIFOs for Voltage/Frequency Island-based Networks-on-Chip

One of the major design bottlenecks in today’s high-performance VLSI systems is the distribution of a single global clock across a chip due to process variability, power dissipation, and multi-cycle cross-chip signaling. A Network-on-Chip architecture partitioned into several Voltage/Frequency Islands (VFIs) is considered as a promising approach for achieving fine-grain system-level power management. In a VFI-based architecture, a clock is utilized for local data synchronization, while inter-island communication is handled asynchronously. To interface the islands on a chip, operating at different frequencies, a complex bi-synchronous FIFO design is inevitable. However, these FIFOs are not needed if adjacent switches belong to the same clock domain. In this paper, a Reconfigurable Synchronous/Bi-Synchronous (RSBS) FIFO is proposed which can adapt its operation to either synchronous or bi-synchronous mode. Four different scalable and synthesizable designs are presented. In addition, a technique is suggested to show how the FIFO could be utilized in a VFI-based NoC. Moreover, we present a mesochronous adaptation method and propose Reconfigurable Mesochronous/Bi-Synchronous (RMBS) FIFOs. Our extensive experiments reveal that compared to a non-reconfigurable system architecture, the proposed reconfigurable FIFOs can help to achieve up to 17% savings in the average power consumption of NoC switches and 29% improvement in the total average packet latency in the case of an MPEG-4 encoder application.

High Performance VLSI Architecture of Bi-directional Motion Search for B Picture in H.264

Bi-directional motion search is one of the important features of B picture coding in H.264/AVC. However, its high computational complexity and huge memory traffic make design difficult. This paper proposes a high throughput and cost efficient VLSI architecture for bi-directional integer motion estimation (Bi-IME). The redundancy of the joint motion search is removed, and the algorithm is simplified. Novel memory structure and intelligent reading method are designed to satisfy the iterations of full search with two reference windows. The parallel and sequence techniques are adopted to process the matching procedure. After logic synthesis using SMIC 0.13 μm standard cell library, under a clock frequency of 300 MHz, the proposed Bi-IME architecture can provide processing capacity up to 149 M MBs/sec which is enough for 1080p real-time video systems.

High performance VLSI design of runbefore for H.264/AVC CAVLD

High-performance algorithm and VLSI architecture for H.264/AVC context-adaptive, variable-length decoder (CAVLD) run_before computations are proposed to reduce the computation cycles. The run_before values of input symbols are estimated if they are zeroes in parallel. By skipping the estimation step when long symbols starting with ‘000’ are input, the architecture was drastically simplified while maintaining high performance. Experimental results showed that the performance for run_before computations improved by 68% on average when four symbols were estimated in parallel in comparison with sequential estimation of the symbols. The area of run_before is increased by 23% by the proposed architecture.

A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect

Gate delay evaluation is always a vital concern for high-performance digital VLSI designs. As the feature size of VLSIs decreases to the nano-meter region, the work to obtain an accurate gate delay value becomes more difficult and time consuming than ever. The conventional methods usually use iterative algorithms to ensure the accuracy of the effective capacitance Ceff, which is usually used to compute the gate delay with interconnect loads and to capture the output signal shape of the real gate response. Accordingly, the efficiency is sacrificed. In this paper, an accurate and efficient approach is proposed for gate delay estimation. With the linear relationship of gate output time points and Ceff, a polynomial approximation is used to make the nonlinear effective capacitance equation be solved without iterative method. Compared to the conventional methods, the proposed method improves the efficiency of gate delay calculation. Meanwhile, experimental results show that the proposed method is in good agreement with SPICE results and the average error is 2.8%.

An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV

Fractional Motion Estimation (FME) in high-definition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various modes and complex mode decision flow, which require over 45% of the computation complexity in the H.264 encoding process. In this paper, a new high-performance VLSI architecture for Fractional Motion Estimation (FME) in H.264/AVC based on the full-search algorithm is presented. This architecture is made up of three different pipeline processors to establish a trade-off between processing time and hardware utilization. The computing scheme based on a 4-pixel interpolation unit with a 10-pixel input bandwidth is capable of processing a macroblock (MB) in 870 clock cycles. The final VLSI implementation only requires 11.4 k gates and 4.4kBytes of RAM in a standard 180 nm CMOS technology operating at 290 MHz. Our design generates the residual image and the best MVs and mode in a high throughput and low area cost architecture while achieving enough processing capacity for 1080HD (1920?×?1088@30fps) real-time video streams.

Power-Estimation for On-Chip VLSI Distributed RLC Global Interconnect Using Model Order Reduction Technique

ABSTRACT Power is increasingly becoming the bottleneck for the design of high performance VLSI circuits. It is essential to analyze how the various components of power are likely to scale in the future, thereby identifying the key problematic areas. While most analyses focus on the timing aspects of interconnects, power consumption is also important. In this paper, the power distribution estimation of interconnects is studied using a reduced-order model [1]. The relation between power consumption and the poles and residues of a transfer function is derived, and an appropriate driver model is developed, allowing power consumption to be computed efficiently. Categories and Subject Descriptors B.7.2 [ Integrated Circuits ]: Design Aids – Simulation; General Terms Algorithms, Design, Theory Keywords Power estimation, Model Order Reduction, RCL Interconnect, Moment matching 1. INTRODUCTION As the scale of process technologies steadily shrinks and the size of designs increases, interconnects have increasing impact on the area, delay, and power consumption of circuits. Over the past decade there have been a number of advances in modeling and the analysis of interconnect that have facilitated the continual advances in design automation for systems of increasing size and frequency. As integrated circuit feature sizes continue to scale well below 0.18 µm [2], active device counts are reaching hundreds of millions. Interconnect models must incorporate distributed self and mutual inductance to accurately estimate time delay and crosstalk in a multilevel network for multi-GHz gigascale integration (GSI) [3]. In addition to interconnect delay, crosstalk noise resulting from capacitive and, more recently investigated, inductive effects [4], [5] between adjacent interconnect lines is also becoming a primary concern for ICs performance and reliability. Furthermore, with present VLSI technology, on -chip interconnects are best modeled as a network of coupled lines the amount of interconnect among the devices tends to grow super linearly with the transistor counts, and the chip area is often limited by the physical interconnect area. Due to these interconnect area limitations, the interconnect dimensions are scaled with the devices whenever possible. In addition, to provide more wiring resources, IC’s now accommodate numerous metallization layers, with more to come in the future. These advances in technology that result in scaled, multi-level interconnects may address the wire ability problem, but in the process create problems with signal integrity and interconnect delay. As regards power, the situation is similar in that the portion of power associated with interconnects is increasing. This is an important fact because the conventional design, analysis, and synthesis of VLSI circuits are based on the assumption that gates are the main sources of on-chip power consumption. Furthermore, the power consumed by interconnects results in a phenomenon, called self heating, which reduces electro-migration induced mean time to failure (MTF) [6]. It is shown in [7] that the power distribution analysis on interconnects is feasible in frequency domain using poles and residues. However, high complexity is inevitable when calculating the power dissipation of the whole interconnects since poles and residues of the current flowing through each element have to be calculated. As feature sizes are decreased to deep sub-micrometer dimensions, on-chip interconnect is best modeled as a distributed RLC line. However, unlike the RC model, such a model increases the complexity of interconnects crosstalk noise and its induced delay estimation. Advances in deep sub-micron technology indicate that present and future interconnects might no longer be considered as simply made of RC lines. Thus, RLC interconnect models become a necessity [8]. It therefore appears that, if accurate interconnect delay estimation is to be achieved, modeling interconnect as a distributed RLC line is necessary. In this case, the commonly and generally well-accepted Elmore delay calculation becomes inapplicable to RLC interconnect networks due to their non-monotonic characteristics induced by inductances [8] [9]. To verify the effects induced by interconnects a combination of extraction and analysis is necessary. Extraction determines the capacitance and the resistance of interconnects, which can then be used to build a circuit model for the analysis of interconnect effects. For analysis (or estimation), extensive studies have been made of the use of model order reduction over the last few years, following the introduction of AWE [9]. Model order reduction is based on approximating the Laplace-domain transfer function of a linear network by a relatively small number of dominant poles and zeros. Such reduced order models can be used to predict the timedomain or frequency-domain response of the linear network. Power, which inherently involves improper integration, can be derived from the poles and residues of the transfer function, which requires only algebraic computation. When the interconnect is driven by MOSFETs and connected to the gates of MOSFETs, the