Characteristics of double-gate SOI CMOS nanotransistors for promising technologies with a low power consumption level

Abstract

A procedure, allowing one to optimize topological and electrophysical parameters of double gate SOI nanotransistors with a thin unalloyed working area, with underlap gate and drain/source regions with regard to the physical restrictions and process requirements, without recourse to the 2D-simulation, is considered. Based on the numerical simulation results, the selection criteria of the key topological parameters of transistors for implementing the requirements in accordance with the International Technology Roadmap for Semiconductor 2010 Edition program for promising applications with a low power consumption level are discussed. The complex analysis of the VACs of transistors and gate characteristics, such as a time switching delay, as well as active and static power, shows that prototypes of the considered units are applicable for implementing high-performance VLSI projects.