Abstract
Motion estimation is the most computationally intensive part of any video coding standard. The three-step search algorithm is a popular fast search technique to reduce complexity in motion estimation. In this paper, we propose a novel architecture for the three-step search technique that simplifies memory addressing and reduces hardware complexity. The proposed architecture minimizes the area while maintaining the speed requirements for real-time video processing. Implemented in Verilog HDL on Virtex-5 technology and synthesized using Xilinx ISE Design Suite 14.1, the critical path in the hardware is 6.536 ns and the equivalent area is calculated to be 2.3 K gate equivalent.
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