High Performance SOI Research Articles

A Novel High Performance SOI LDMOS with Buried Stepped Gate Field Plate

A Novel High Performance SOI LDMOS with Buried Stepped Gate Field Plate

Research of single event burnout in a high-performance radiation-hardened SOI lateral power MOSFET

In this paper, a 60 V radiation-hardened SOI lateral power MOSFET (LDMOS) device is proposed and single event burnout (SEB) failure mechanism of the device is investigated by Sentaurus simulator. The SOI LDMOS device, with 2 μm drift region and extended N+ drain region, can achieve optimal breakdown voltage (BVDS, 67 V) and specific on-resistance (Ron,sp, 5 mΩ·cm2), while Ron,sp of the device without extended N+ drain is 5.6 mΩ·cm2. Sensitive region of the device for SEB is analyzed and the most sensitive region for SEB is near the center of drift region. The influence of different linear energy transfers (LETs) on SEB threshold voltage is explored and the device can survive at the full drain to source voltage (VDS) biasing of 60 V even for a highly-energetic ion with LET of 1 pC/μm (96 MeV·cm2/mg). Besides, heavily-doped P+ region is inserted on the source side and parameters of source region are optimized to improve SEB tolerance of the device. Second breakdown voltage of the device which correlates with SEB failure threshold is up to 66 V, indicating excellent SEB hardness of the device. Eventually, SEB failure mechanism of the device is investigated in detail and the action of the parasitic npn bipolar junction transistor (BJT) inherent in the device structure is the key to SEB tolerance of the device.

Analysis and performance exploration of high performance (HfO2) SOI FinFETs over the conventional (Si3N4) SOI FinFET towards analog/RF design

Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs (short channel effects) in sub 22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2 (conventional HfO2 spacer SOI FinFET) and device-D3 (source/drain extended HfO2 spacer SOI FinFET) over the device-D1 (conventional Si3N4 spacer SOI FinFET) at 20 nm technology node through the 3-D (dimensional) simulation process. The major performance parameters like Ion (ON current), Ioff (OFF current), gm (transconductance), gd (output conductance), AV (intrinsic gain), SS (sub-threshold slope), TGF = gm/Id (trans-conductance generation factor), VEA (early voltage), GTFP (gain trans-conductance frequency product), TFP (tans-conductance frequency product), GFP (gain frequency product), and fT (cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation, device-D3 and D2 give better results in terms of gm, ID (drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of fT, GTFP, TFP, and GFP parameters both at low and high values of VDS = 0.05 V and VDS = 0.7 V respectively.

LeTrungThanh Optical Biosensors Based on Multimode Interference and Microring Resonator Structures

LeTrungThanh Optical Biosensors Based on Multimode Interference and Microring Resonator Structures

Novel high-performance SOI junctionless FET-based phototransistor using channel doping engineering: Numerical investigation and sensitivity analysis

In this paper, graded channel doping (GCD) and junctionless paradigms are proposed as a new ways to improve the optical controlled field effect transistor (OCFET) and bridging the gap between the high responsivity and ultra-low power consumption. A careful mechanism study based on numerical investigation and a performance comparison between the proposed structure and both the conventional inversion mode (IM-OCFET) and the junctionless (JL-OCFET) designs is presented. It is found that the graded channel doping feature can efficiently improve the overall device optical and electrical performances. Moreover, the proposed design exhibits superior device figures of merit (FoMs) and provides ultra-sensitivity behavior as compared to both the conventional IM-OCFET and the JL-OCFET counterparts. Our investigation reveals also the outstanding capability of the proposed structure for offering the weak signal detection advantage that demonstrates the unique property of our phototransistor with GCD aspect. These characteristics not only underline the excellent switching behavior of the proposed design but also demonstrate the ability for overcoming the trade-off between the low cost and readily fabrication process in addition to ultrasensitive aspect with low power consumption. This makes the proposed GCD-JL-OCFET a potential alternative for developing low power communication systems.

High-performance SOI MESFET with modified depletion region using a triple recessed gate for RF applications

A novel SOI MESFET with the modified depletion region using a Triple Recessed Gate (TRG-SOI MESFET) is presented for RF applications. The proposed gate consists of lower and upper gate to control the channel thickness and the depletion layer will change by omitting part of total charge due to locating gate in the channel. The key idea of this shaped gate is to modify the depletion region and the charge distribution of the channel in order to lower the electric field of the device and improving the breakdown voltage. In addition the maximum power density, the maximum oscillation frequency, the cutoff frequency, and the minimum noise figure for the proposed structure are improved due to increasing the drain-source resistance and the transconductance and decreasing the gate resistance. Therefore, the TRG-SOI MESFET can be used for high-power and high frequency applications.

High performance SOI CMOS pixel sensor with surrounding N+ trench electrode

In this paper, an advanced SOI CMOS pixel (ASCP) detector structure with deep N+ trench electrode is researched and simulated. For this pixel structure, the N+ trench cathode surrounds the P+ trench anode, and they are both connected from the topside. The cathode is in the function of charge share shielding, it isolates the neighbor pixels, and avoids the crosstalk happening of electron hole pairs. Furthermore, the parallel trench electrodes between anode and cathode have reduced the fully depleted voltage, and the bias voltage can be controlled from the core I/O interface. In addition, the ASCP has the better radiation resistance capacity as compared with the Conventional SOI CMOS pixel detector and the Three-Dimension (3D) CMOS detector, due to the low fully depleted voltage and short carrier drift distance. Numerical simulation results show that the ASCP detector has the better charge collecting capacity in low driving voltage, and it is more suitable to detect the back-illumination X-ray 55Fe.

Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved f<SUB>t</SUB>BV<SUB>CEO</SUB> product (397 GHzV). As the BV<SUB>CEO</SUB> value is higher for low value of epi layer doping, higher supply voltage can be used to increase the ft value of the HBT. At 1.8 V V<SUB>CE</SUB>, the f<SUB>t</SUB>BV<SUB>CEO</SUB> product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV f<SUB>t</SUB>BV<SUB>CEO</SUB> product at 1.2 V V<SUB>CE</SUB>). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

Design, fabrication and characterization of high performance SOI MEMS piezoresistive accelerometers

Piezoresistive accelerometers have served as the frontrunners in micromachined accelerometer technology and have undergone modifications with the primary focus on device complexity and novel processes to circumvent performance trade-offs. This work comprises the analysis, design and development of micromachined SOI MEMS-based piezoresistive accelerometers for inertial sensing applications using minimalistic component design and a custom fabrication process to realize robust devices capable of withstanding more than ~106 cycles of error-free operation. Extensive simulation studies have been carried out to validate and tune the design parameters of the analytical models used. The devices have been subjected to an exhaustive range of static and dynamic tests to characterize their response which has been sensitive and highly linear with low noise, an intrinsic quality of piezoresistive sensors coupled with precision design and fabrication.

A Novel RF SOI LDMOS with a Raised Drift Region

In this paper, we propose a novel RF SOI LDMOS with a raised drift region (RDR). Using the process simulation and numerical simulation, we investigate deeply on breakdown characteristics and frequency characteristics of this novel device. Compared with the conventional RESURF device, the breakdown voltage and cutoff frequency of the RDR device are increased by 25% and 21%, respectively. The work of this paper has theoretical and practical significations to the research of a new generation of deep sub-micron high-performance radio frequency SOI integrated circuits.

Comparison of MOCVD- and ALD-Deposited $ \hbox{HfZrO}_{4}$ Gate Dielectrics for 32-nm High-Performance Logic SOI CMOS Technologies

For the first time, <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{HfZrO}_{4}$</tex></formula> dielectrics deposited with metal–organic chemical vapor deposition (MOCVD) as well as atomic layer deposition (ALD) have been investigated as high- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$k$</tex></formula> gate dielectric for 32-nm high-performance logic SOI complementary metal–oxide–semiconductor devices in this letter. The composition of the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{HfZrO}_{4}$</tex></formula> films has been analyzed in detail by atom probe tomography, Rutherford backscattering spectrometry, and X-ray photoelectron spectroscopy. Optical inline measurements and electrical parameters such as gate leakage current, capacitance equivalent thickness, threshold voltage, and performance as well as reliability data have been taken into account to directly compare both deposition methods. All parameters indicate a comparable behavior for MOCVD and ALD. Therefore, MOCVD has been demonstrated to be a promising alternative to ALD in high-volume manufacturing.

Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology

For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high temperature, the power consumption of such circuits is completely dominated by static power dissipation due to leakage currents. In this contribution, we propose a new logic style, namely ultra-low-power (ULP) logic style which achieves negative V gs self-biasing, to benefit from the small area and low dynamic power of high-performance deep-submicron SOI technologies while keeping ultra-low leakage, even at high temperature. In 0.13 μm partially-depleted SOI CMOS technology, the static power consumption at 200 °C is reduced by nearly three orders of magnitude at the expense of increased delay and area.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin.

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V

The 65 nm cell broadband enginetrade (cell BE) is a multi-core SoC, implemented in a high performance SOI technology featuring a separate dual power supply for SRAM arrays to improve stability and performance using an elevated voltage. A new method is shown to analyze the SRAM cell under application conditions which was used to tune the cell for stability, write-ability and performance. An improved write scheme is shown which widens the overall functional window and allows setting the power/performance point of the arrays independently of the surrounding logic. Hardware measurements demonstrate the advantages of the dual power supply under different aspects.

High Performance SOI Technology for Sub-45nm Gate Length CMOS Manufacturing

not Available.

High-performance p-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions

A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.

High-performance fully-depleted SOI RF CMOS

A T-gate structure has been implemented in the fabrication of fully depleted silicon-on-insulator MOSFETs. The T-gate process is fully compatible with the standard CMOS and the resulting reduction of gate-resistance significantly improved the RF performance. Measured f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> is 76 GHz and 63 GHz for n- and p-MOSFET with 0.2-μm gate length, respectively. At 2 GHz, a minimum noise figure of 0.4 dB was measured on an n-MOSFET with the T-gate structure.

The spacer/replacer concept: a viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS

We introduce the Spacer/Replacer concept, a new concept to improve the device performance of ultrathin-film fully-depleted (FD) SOI CMOS transistors. High-performance FD SOI CMOS transistors are demonstrated with a silicon film thickness of 30 nm and physical gate-lengths down to 0.1 μm. The approach uses selective epitaxial growth of silicon to form raised source/drains while avoiding the simultaneous formation of a T-shaped poly-Si gate. In addition, the introduced concept eases the integration issues related to the ultrathin silicon film.

A high-performance SOI drive-in gate controlled hybrid transistor (DGCHT)

A novel SOI drive-in gate controlled hybrid transistor is put forward in this paper. Compared with previous hybrid transistors, with the former advantages retained, drive-in gate controlled hybrid transistor (DGCHT) can obtain short channel without any submicron technology. And the Early voltage can be increased in spite of the depleted base surface. The breakdown characteristics can be improved in spite of the shorter channel length and the high current gain.

Wafer bonding: SOI, generalized bonding, and new structures

Wafer bonding in semiconductor technology is reviewed. Potential applications of this technique, already demonstrated in research labs, range from high performance SOI CMOS circuits and high voltage or power devices to on-chip microsensors and integration of III–V materials with Si substrates. A summary of the bonding kinetics, as well as methods of the device film formation is given. The quality of the film is discussed, along with common problems encountered in this technology.