The spacer/replacer concept: a viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS

Abstract

We introduce the Spacer/Replacer concept, a new concept to improve the device performance of ultrathin-film fully-depleted (FD) SOI CMOS transistors. High-performance FD SOI CMOS transistors are demonstrated with a silicon film thickness of 30 nm and physical gate-lengths down to 0.1 μm. The approach uses selective epitaxial growth of silicon to form raised source/drains while avoiding the simultaneous formation of a T-shaped poly-Si gate. In addition, the introduced concept eases the integration issues related to the ultrathin silicon film.