High-performance Bipolar Transistors Research Articles

Investigation of Residual Strain in 4H-SiC/Si Heterostructures Fabricated By Surface Activated Bonding

Silicon carbide (SiC) is one of the most potential materials for the next generation power devices because of its advantageous material properties and the maturity of processing technology. SiC/Si heterojunction is a potentially useful system for realizing high-performance bipolar transistors with wide band gap emitters, switching devices, electroluminescence devices, and sensors. On the other hand, it is difficult to grow SiC on Si due to the large mismatch in the lattice constant and the thermal expansion coefficients between Si and SiC. We previously fabricated 4H-SiC/Si junctions using surface activated bonding (SAB) method and investigated their electrical characteristics. It was found that the electrical properties of 4H-SiC/Si junctions improved with increasing annealing temperature and the amorphous layer formed at the interface without annealing vanished after the interface annealing at 1000 °C. It is possible to fabricate 4H-SiC/Si junctions at room temperature due to the amorphous layer absorbed the residual stresses caused by the mismatch in the lattice constant. However, the stress state of the bonded interface with annealing at 1000 °C is not clear after the recrystallization of the amorphous layer. The knowledge of the stress state near the bonded interface is very important for better understanding the vibrational properties and improving the electrical properties of the devices fabricated by SAB.In this work, the residual stress near the 4H-SiC/Si bonded interface was investigated using confocal micro-Raman scattering technique. The effects of thermal annealing process on the residual stress of the bonded interface were also investigated. The magnitude of the residual stress near the bonded interface was calculated from the measured frequency shift with respect to the stress-free Raman peak position. The structural properties of the bonded interfaces were examined by transmission electron microscopy (TEM) observation.B–doped (100) p+-Si substrate and n-4H-SiC epitaxial substrates (6 um, 5 × 10E15 cm-3 epitaxial layer / 0.5 um, 1 × 10E18 cm-3 buffer layer / substrate 3 × 10E18 cm-3) were used for the bonding experiment. Si and 4H-SiC substrates were bonded to each other by SAB. And then, the bonded samples were annealed separately at 400, 700, and 1000 °C for 60 s in N2 gas ambient. The residual stress in 4H-SiC/Si heterostructures was systematically investigated by micro-Raman spectroscopy. Micro-Raman mapping measurement was performed for an area of 40 × 40 μm2 with a step of 2 μm. A Renishaw InVia confocal micro-Raman spectroscopy measured under backscattering geometry, an Ar+ laser of 488 nm, a diffraction grating of 2400 lines/mm, a 50× long working distance objective lens, and a laser sport size of about 1.5 μm was used. 4H-SiC and Si peak frequencies were determined using the curve-fitting option integrated in the operation software by performing a Lorentz fitting to the spectral. The accuracy of the peak frequency is within ±0.02 cm-1. The interfacial structures of the bonded samples were investigated using TEM (JEM-2200FS)The Raman peak shift mappings of 4H-SiC E2 (TO) and Si phonon mode in 4H-SiC/Si heterostructures without annealing are shown in Fig. 1(a) and 1(b), respectively. The averaged Raman peak shift position for SiC and Si is observed to be 776.57 and 519.86 cm-1, respectively. A uniform distribution of Raman peak position is obtained for both SiC and Si phonon modes. The stress state of SiC and Si can be considered nearly stress free in 4H-SiC/Si heterostructures with respect to their bulk counterpart values of 4H-SiC and Si substrate at 776.54 and 519.93 cm-1, respectively. This result indicates that stress free 4H-SiC/Si heterostructures was achieved by SAB method. Figure 1

Impact of lateral and vertical scaling on the reliability of a low-complexity 200 GHz SiGe:C HBT

As device scaling for high-performance bipolar transistors continues, not only the vertical scaling but also the lateral scaling with reduction of the parasitics can have an important impact on the reliability of the HBT. In this work we will present the impact on the RF performance and the reliability of the vertical and lateral scaling of a SiGe:C HBT with a low-complexity QSA (quasi self-aligned) architecture. The reliability will be assessed for three different stress modes.

1677 V, 5.7 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC BJTs

This letter reports the development of a high-performance power 4H-SiC bipolar junction transistor (BJT) with, simultaneously, a high blocking voltage and a low specific on-resistance (R/spl I.bar//sub ON/). A single BJT cell with an active area of 0.61 mm/sup 2/ achieves an open base collector-to-emitter blocking voltage (V/sub ceo/) of 1677 V and conducts up to 3.2 A at a forward voltage drop of V/sub CE/=3.0 V, corresponding to a low R/spl I.bar//sub ON/ of 5.7 m/spl Omega//spl middot/cm/sup 2/ up to Jc=525 A/cm/sup 2/ and a record high value of V/sub B//sup 2//R/sub SP/spl I.bar/ON/ of 493 MW/cm/sup 2/.

Herb's bipolar transistors

The profound influence of Herbert Kroemer's ideas on the development of high-performance bipolar transistors is described. The historical context and subsequent development of innovations such as the drift base, achieved through concentration gradients and later with semiconductor bandgap grading, the use of wide bandgap emitters, concepts of collector-up transistors, and the introduction of new heterojunction materials, are reviewed.

Optical characterization and metal–nonmetal transition of boron-doped Si 1− xGe x alloy

We report measurements of the optical band gap of Si 1− x Ge x , by photoacoustic spectroscopy technique. The material has been obtained by a mechanical alloying process. Due to its technological application, in high-performance bipolar transistors and integrated circuits, the interest in the physical properties of Si 1− x Ge x has recently increased. The metal–nonmetal transition (for x=0.2) is determined to be 3.2×10 18 cm −3. The optical band gap estimated from the absorption data at high boron concentration shows band gap narrowing when compared to the undoped alloy.

High-quality n-Si/i-p+-i SiGe/n-Si structure grown by ultra high vacuum chemical molecular epitaxy

The n-Si/i-p+-i SiGe/n-Si structure was grown by ultra high vacuum chemical molecular epitaxy, and analysed by high resolution X-ray diffraction, cross-sectional transmission electron microscopy, and secondary ion mass spectroscopy. A high-quality SiGe base layer with an abrupt interface to the Si was obtained. No defects were observed in the n-Si/i-p+-i SiGe/n-Si structure. Both the Ge and boron atoms are uniformly distributed in the p+-SiGe layer, and the changes of profile of both boron and Ge atoms are abrupt from the n-Si to the SiGe layer. A high-performance microwave power SiGe heterojunction bipolar transistor (HBT) was made from the n-Si/i-p+-i SiGe/n-Si structure. Therefore, device-quality n-Si/i-p+-i SiGe/n-Si structures can be grown by ultra high vacuum chemical molecular epitaxy.

0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation

Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-/spl mu/m RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFET's maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications.

Optical properties of bonded silicon silicide on insulator (S 2OI): a new substrate for electronic and optical devices

A new type of silicon on insulator substrate was fabricated using wafer bonding. The inclusion of a highly conducting buried tungsten silicide layer below the silicon device layer but above the oxide film results in many attractive properties for electronic and optical devices such as high performance bipolar transistors, power devices and optoisolators. Commercial products are being developed using this new S 2OI material. However, to fully exploit this material a detailed understanding of its optical and physical nature is required. To this end a study of the buried silicide film, its interfaces and the overlying silicon was carried out using spectroscopic ellipsometry and atomic force microscopy. It was found that the buried silicide undergoes a structural transformation, due to the thermal bonding anneal, resulting in a rough interface between it and the silicon overlayer.

CMOS transconductance multipliers: a tutorial

Real time analog multiplication of two signals is one of the most important operations in analog signal processing. The multiplier is used not only as a computational building block but also as a programming element in systems such as filters, neural networks, and as mixers and modulators in a communication system. Although high performance bipolar junction transistor multipliers have been available for some time, the CMOS multiplier implementation is still a challenging subject especially for low-voltage and low-power circuit design. Despite the large number of papers proposing new CMOS multiplier structures, they can be roughly grouped into a few categories. This tutorial provides a complete survey of CMOS multipliers, presents a unified generation of multiplier architectures, and proposes the most recommended MOS multiplier structure. This tutorial could serve as a starting reference point (and metric) for comparison of new CMOS multiplier circuit configurations. An illustrative CMOS chip prototype verifying theoretical results is presented.

The SCC BJT: a high-performance bipolar transistor compatible with high-density deep-submicrometer BiCMOS SRAM technologies

We present the process development and device characterization of the Selectively Compensated Collector (SCC) BJT specifically designed for high-density deep-submicrometer BiCMOS SRAM technologies. This double-poly BJT takes advantage of the self-aligned polysilicon layers of the SRAM bit cell to obtain high performance without adding excessive process complexity. Furthermore, although an NPN device, the SCC BJT is formed in a lightly doped p-well in which the collector is formed with a single 370 keV phosphorus implant to minimize parasitic junction capacitances without the use of trench isolation or recessed oxides. The suitability of this bipolar structure outside of its original FSRAM intent is proven with its potential for bipolar logic and mixed-mode RF applications. ECL delays of 50 ps at 200 /spl mu/A and a CML power-delay product of 4.5 fJ at 1.1 V supply were obtained. A 900 MHz noise figure as low as 0.54 dB at 0.5 mA with an associated gain of 14.7 dB was demonstrated as well as a dual modulus /spl divide/4/5 prescaler operating up to 3.3 GHz for a switch current of 200 /spl mu/A.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new test structure for the evaluation of graft-base lateral diffusion depth in high-performance bipolar transistors

A new test structure allows the first electrical measurement of lateral diffusion depth of the graft base in high-performance bipolar transistors. It is indispensable for realizing high cutoff frequency to control the graft-base depth. The test structure has two independent base electrodes and no emitter region. It can evaluate the effective intrinsic-base length by measuring resistance between two electrodes. Graft-base depth can be derived from the active-base length and the effective intrinsic-base width. The feasibility of this structure Is confirmed by evaluating 50-GHz and 30-GHz transistors, with graft-base depths of 0.05 /spl mu/m and 0.13 /spl mu/m, respectively. The new method is compared with conventional ones. >

High-performance SiGe epitaxial base bipolar transistors produced by a reduced-pressure CVD reactor

High-performance Si and SiGe epitaxial base bipolar transistors have been fabricated using a commercially available, reduced pressure, epitaxial reactor. The SiGe devices exhibit exceptional Early voltages in the range of 400-500 V, and an f/sub T/ of 31 GHz with a BV/sub CEO/ of 7.6 V and BV/sub CBO/ of 16 V. These results demonstrate that SiGe has potential as a commercially viable technology for analog, digital, and mixed-signal applications. >

Implant-induced strain-relaxation in SiGe/Si layers

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. SiGe is typically used as an epitaxial base material in HBTs. To obtain extremely high-performance bipolar-transistors it is necessary to reduce the extrinsic base-resistance. This can be done by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however with the use of implantation is that blanket implants have been found to enhance strain-relaxation of SiGe/Si. Strain relaxation will cause the bandgap-difference between Si and SiGe to decrease; this difference is maximum for a strained SiGe layer. The electrical benefits of using SiGe/Si arise largely from the presence of a significant bandgap-difference across the SiGe/Si interface. Strain relaxation reduces this benefit. Furthermore, once misfit or threading dislocations result (during strain-relaxation), the defects can give rise to recombination-generation in depletion regions of the device; high electrical leakage currents result.

A 64-GHz f/sub T/ and 3.6-V BV/sub CEO/ Si bipolar transistor using in situ phosphorus-doped and large-grained polysilicon emitter contacts

A high-performance bipolar transistor has been developed using an in-situ phosphorus doped polysilicon (IDP) technique for emitter formation. The transistor demonstrated in ultrahigh current gain of 700, a maximum cutoff frequency f/sub T(max)/ of 64 GHz, and a breakdown voltage between collector and emitter BV/sub CEO/ of 3.6 V. At V/sub CE/ values of 2 and 3 V, a product of f/sub T(max)/ and BV/sub CEO/ of 200 GHz-V has been achieved. This value is nearly equal to the physical limitation for homojunction silicon transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Formation of defects in boron-implanted PEPBLT structures

Variations on LOCOS (local-oxidation of silicon) are being explored for device-isolation, to implement further miniaturization of VLSI devices. One such variation involves poly-encapsulated poly-buffered LOCOS + trench-isolation (PEPBLT). The method provides a means to support device scaling and to create self-aligned shallow field-oxide elements with minimal encroachment into active regions. In an earlier study, dislocations were observed to be associated with a combination of high-dose ∼1E15 cm−2 phosphorus implants and PEPBLT isolation. The present study investigates the effect of boron implants on similar PEPBLT structures. The effect of fabrication-related stresses in the structures is of interest because extended-defects, if formed, could electrically degrade transistors.PEPBLT structures were exposed to varied processing conditions to build high-performance bipolar transistors. Isolated active-device regions from the above structures were characterized using TEM. Some of the active regions were (i) implanted with 80 keV-8.5E15 cm−2 boron with no anneal, (ii) implanted with 80 keV- 8.5E15 cm−2 boron and annealed at 900°C/90’/N2 plus 1050°C/30” RTA during the course of processing, (iii) not implanted.

A two-step implanted base (TSIB) process for high-performance bipolar transistor

The fabrication process, device profiles, and electrical characteristics of an advanced bipolar transistor with a two-step ion-implanted base (TSIB) are described. This base implant scheme has achieved a significant collector-emitter leakage yield improvement over the conventional transistor (control) which does not receive the TSIB implant. The TSIB base profile can be kept almost identical to that of the control transistors by using the selective implanted collector process. The maximum cutoff frequency of 20 GHz is measured.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Effect of reverse base current on bipolar and BiCMOS circuits

A detailed study on the effect of reverse base current (RBC) on the switching behavior of bipolar BiCMOS circuits utilizing advanced high-performance bipolar transistors is presented. It is shown that as the collector doping N/sub c/ is increased to overcome the Kirk effect (base stretching) during the switching transient, the avalanche-generated reverse base current in the collector-base junction may cause problems for bipolar output devices switching out of saturation. A basic bipolar inverter and various BiCMOS driver circuits were simulated based on measured avalanche multiplication factors from advanced bipolar transistors with various collector doping N/sub c/. In the case of the basic bipolar inverter, the reverse base current may prevent the switching device from being shut off completely during the on-to-off transition and a self-sustained state may result which reduces the output voltage swing. For the common-emitter (CE) BiCMOS driver, a similar self-sustained state may also occur with the added adverse effect of excessive leakage in standby. Design and scaling considerations are discussed. >

A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications

A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process. >

The implementation of a reduced-field profile design for high-performance bipolar transistors

The first realization of a reduced-field design concept for advanced bipolar devices using the low-temperature epitaxial (LTE) technique to form the base layer is described. By inserting a lightly doped collector (LDC) spacer layer between the heavily doped base and collector regions, it is successfully demonstrated that the collector-base (CB) junction avalanche multiplication can be reduced substantially while maintaining high collector doping for current density consideration. Similar applications of the LDS technique to the emitter-base (EB) junction also results in a lower electric field, thus less EB junction reverse leakage. The feasibility of the reduced-field profile design concept is demonstrated using a LTE-base device structure. >

Dependence of current gain β on spacer geometry and emitter size in polysilicon self-aligned bipolar transistors

For self-aligned bipolar technologies the sidewall region under the residual spacer, which is very much influenced by the spacer geometry, is a key feature. We have investigated the effect of the spacer geometry on the transistor performance, especially on the current gain β. The spacer geometry is arranged by varying its width separating the n + and p + lateral diffusions and by varying its depth penetrating into the monocrystalline silicon. It has been found that these two variations do not cause the same effect on β. Although the increase of both the spacer isolation depth and width causes an increase in β, β has an enhanced dependence on the spacer depth. This latter finding sets a limitation on the maximum spacer depth for the high performance bipolar transistors. A 2-D simulation is performed to demonstrate these effects.