A 0.8- mu m advanced single-poly BiCMOS technology for high-density and high-performance applications

Abstract

A single-poly, 0.8- mu m advanced BiCMOS technology, ABiC IV, is described. It has both high-performance CMOS and 15-GHz bipolar transistors. The process described has been developed for high-performance application-specific IC (ASIC) applications with emphasis on embedded CMOS, BiCMOS, or emitter-coupled logic (ECL) memory as well as BiCMOS and ECL gate arrays and standard cells. The key features of this BiCMOS process are twin buried layers, low encroachment recessed oxide isolation, a double-diffused bipolar process, a single-poly architecture with silicided local interconnection, and four levels of metallization with tungsten plugs. Ring-oscillator gate delays of about 125 ps for BiCMOS, less than 90 ps for CMOS, and about 48 ps for ECL were obtained with this process. >