Abstract
A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden
Published Version
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https://doi.org/10.1109/jssc.2025.3526595
Copy DOIJournal: IEEE Journal of Solid-State Circuits | Publication Date: Jan 1, 2025 |
A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden
Join us for a 30 min session where you can share your feedback and ask us any queries you have
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