Asynchronous SAR logic design using majority vote comparison for configurable SAR ADCs

Abstract

A low-power configurable design for an asynchronous SAR ADC that is suitable for analog front-end of sensor ASICs is presented. The proposed architecture employs a majority vote based comparator capable of providing programmable noise performance. The proposed asynchronous digital logic determines the majority vote by employing two counters at the comparator differential output. Simulation result shows that the total number of votes in a 12-bit ADC can be reduced by 42% using a split-counter majority voter. Further reduction is possible by allocating the number of votes non-uniformly with more votes closer to LSB cycles. Simulation results show that the total number of votes can be reduced by 65% in a 12-bit ADC with the non-uniform vote allocation. When compared to a non-voting conventional 12-bit SAR ADC with the same overall performance, the comparator power is reduced by 46%.