An advanced 0.4 mu m BiCMOS technology for high performance ASIC applications

Abstract

An advanced 0.4 mu m BiCMOS technology has been developed for high-performance ASIC (application-specific integrated circuit) applications. The technology consists of a core 3.3 V CMOS process featuring 0.4 mu m effective channel lengths into which a high-performance n-p-n device module has been integrated. The ECL (emitter coupled logic) circuits are designed to operate with a conventional supply voltage of 5.2 V while the CMOS circuits are powered from an internally regulated 3.3 V supply. The n-p-n device features trench isolation and a self-aligned polysilicon emitter-base structure with a 0.4 mu m final emitter width. A peak Ft of 20 GHz and a minimum ECL delay of 41 ps at Ig=300 mu A have been achieved. This technology features silicided polysilicon local interconnection and up to 4 layers of metallization. A 51 mu m/sup 2/ 6T CMOS SRAM cell is available for applications requiring embedded SRAM. >