Abstract
Submicrometer CMOS devices were integrated with self-aligned double-polysilicon bipolar devices, showing a cutoff frequency of 16 GHz and an ECL circuit speed of 65 ps/gate. It was found that an amorphous silicon film deposited at 575 degrees C and used as the base electrode improve the gate oxide breakdown voltage compared to a polysilicon film deposited at 600 degrees C. The PMOS FETs showed good short-channel behavior for effective channel lengths down to 0.6 mu m, while the NMOS FETs showed a hump in subthreshold current. This hump was eliminated by minimizing the overetch during the base polysilicon reactive-ion-etching process. Minimum-cell CMOS, BiCMOS and bipolar ECL (emitter-coupled logic) circuits were characterized as functions of loading capacitance, power dissipation, power supply voltage, and channel length of the MOS devices. The relative circuit speed improvements in the BiCMOS and CMOS circuits as the channel lengths were scaled from 0.8 mu m to 0.4 mu m were almost the same, while the BiCMOS circuit speed became slower than that of the CMOS when the power supply voltage was reduced below 3.3 V. >
Published Version
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