Modelling and testing for bridging faults in CMOS and BiCMOS combinational circuits

Abstract

Transistor level models and testing methodologies are developed for detecting the bridging faults in CMOS and BiCMOS circuits. The quiescent power supply current (IDDQ) is utilized as the basis of modelling and test generation. Multiple and single bridging faults are covered. Modelling and testing techniques are presented. The first technique employs a new model called the Current Transfer Function (CTF) that is used to detect the bridging faults in CMOS and BiCMOS circuits. The CTF is a Boolean representation of the IDDQ flow path in terms of input variables and transistor topology of a circuit. The other technique employs an extension of the logic transistor function (LTF) model that was developed earlier for detection of transistor stuck faults. This technique is used for modelling and generating the test for single bridging faults in CMOS circuits, as it is simpler and efficient. However, because of certain limitations this technique is not extended for bridging faults in BiCMOS circuits and the multiple bridging faults in CMOS circuits. The CTF and LTF are automatically generated by the path algebra technique.