High-performance Bipolar Transistors Research Articles

Comments, with reply, on A reduced-field design concept for high-performance bipolar transistors by D.D. Tang and P.-F. Lu

The comments point out to the authors of the original work (see ibid., vol.10, p.67-69, 1989) a body of work carried out at Bell Laboratories in the 1950s that underlies their development insofar as collector-base junctions are concerned. Particular attention is given to the work of J.M. Early (1952, 1954). A reply is included.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A reduced-field design concept for high-performance bipolar transistors

A device profile design concept that reduces the junction field, and thus the high-field induced leakage currents as well as the avalanche current, is described. The insertion of an i-layer of thickness equal to the depletion-layer width of the original n/sup +/-p/sup +/ junction can lower the junction field by about a factor of two. Computer studies show that using this design, the collector avalanche current can be reduced by more than one order, while compromising little in the switching speed of the transistor. >

Design considerations of high-performance narrow-emitter bipolar transistors

The control of the lateral diffusion of the extrinsic base is a key issue in the downscaling of high-speed bipolar transistors for achieving the lowest base resistance without altering the shallow impurity profile of the intrinsic region. This letter will present the effects of lateral encroachment of the extrinsic-base dopant on the characteristics of transistors with submicrometer emitter stripe width, measurement of the amount of encroachment, and its relationship to the vertical profile.

A fine emitter transistor fabricated by electron-beam lithography for high-speed bipolar LSI's

A highly stable, high-performance bipolar transistor with a 1/4-µm emitter is developed. This is accomplished by using advanced electron-beam (EB) lithography and polysilicon reactive ion etching (RIE). Results show that the minimum emitter width is only 0.2 µm and the emitter width accuracy is ±0.06 µm. In addition, the gate delay is reduced from 190 to 100 ps/gate for 25-stage, three-input ECL circuits. The effects of an ultra-narrow emitter on transistor characteristics are also studied.

Effects of collector epitaxial layer on the switching speed of high-performance bipolar transistors

The importance of the epitaxial layer in designing the scaled-down high-performance bipolar transistors is well accepted, but its effect on the performance of the conventional switching transistors for logic application is not quite observable, because it is usually overwhelmed by the large parasitics of these devices. For self-aligned transistors having very small parasitics, its effect becomes so significant that it is observable in the power-delay characteristics of the switching circuits. We built self-aligned transistors on epitaxial layers of different thicknesses. The measured switching speed of transistors with thicker epitaxial-collector layers is faster at lower currents due to the lower collector capacitance; but it is slower at higher currents due to the base stretching. The present experimental results provide direct confirmation of the design theory [1].

IIIB-6 high performance bipolar transistors in a CMOS process

IIIB-6 high performance bipolar transistors in a CMOS process