High-k Oxide Research Articles

Advances in La-Based High-k Dielectrics for MOS Applications

This paper reviews the studies on La-based high-k dielectrics for metal-oxide-semiconductor (MOS) applications in recent years. According to the analyses of the physical and chemical characteristics of La2O3, its hygroscopicity and defects (oxygen vacancies, oxygen interstitials, interface states, and grain boundary states) are the main problems for high-performance devices. Reports show that post-deposition treatments (high temperature, laser), nitrogen incorporation and doping by other high-k material are capable of solving these problems. On the other hand, doping La into other high-k oxides can effectively passivate their oxygen vacancies and improve the threshold voltages of relevant MOS devices, thus improving the device performance. Investigations on MOS devices including non-volatile memory, MOS field-effect transistor, thin-film transistor, and novel devices (FinFET and nanowire-based transistor) suggest that La-based high-k dielectrics have high potential to fulfill the high-performance requirements in future MOS applications.

Molecular beam epitaxy, atomic layer deposition, and multiple functions connected via ultra-high vacuum

Molecular beam epitaxy (MBE) invented for the growth of compound semiconductors in the 70’s has been successfully extended to the advanced growth of metals, oxides, oxide/semiconductor interfaces and emergent topological materials by our endeavor in the past three and half decades. In the 80’s, Kwo et al. have invented metal MBE and oxide MBE methods in pioneering spintronics and high-temperature superconducting oxide films. In driving compound semiconductors for optoelectronics, Hong et al. have produced distributed Bragg reflectors with a continuously graded composition between each constituent without shutter operation, and greatly reduced the electrical resistance; this simple method has made easy manufacture of vertical-cavity surface-emitting lasers. In the 90’s, combining (In)GaAs and oxide MBE chambers via ultra-high vacuum, Hong et al. were the first to unpin the Fermi level in oxide/GaAs, which led to the first demonstration of inversion-channel (In)GaAs metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs). Integrating MBE, atomic layer deposition (ALD), and many other functions in ultra-high vacuum, advances have been made in pushing ultimate complementary MOS (CMOS) of record-high device performances and beyond in growing emergent topological materials for spintronics. Our novel method in preserving as-grown (In)GaAs surfaces and interfaces with high-κ oxides and metals enables employing in-situ synchrotron radiation photoemission to study electronic structures in an atomic scale.

Room-temperature solution-processed, ZrOx-based hybrid gate dielectrics for low-voltage organic thin-film transistors on plastic substrates

For advanced electronic device applications including printable, flexible organic electronics and bioelectronics, it is crucial to develop novel dielectric materials with high dielectric strength and low-temperature processability compatible with plastic substrates for producing flexible and low-voltage organic thin-film transistors (OTFTs). Herein, we report the facile fabrication of rationally designed, high-capacitance hybrid gate dielectric films for low-voltage OTFTs on plastic substrates via a room-temperature solution process. To create room-temperature-processed gate dielectrics with high dielectric strength, we designed organic-inorganic hybrid gate dielectric films by including ZrOx networks as inorganic high-k oxide materials for obtaining large capacitance and 1,6-hexanediol diacrylate as a bifunctional UV cross-linking agent and a flexible organic component for increasing the density and flexibility of films and ensuring room-temperature processability. The UV cross-linked ZrOx-based hybrid composite films with a 15 nm thickness showed excellent dielectric properties with a leakage current density of ∼10−6 A/cm2 and a capacitance of 640 nF/cm2. The film surfaces were modified with hydrophobic self-assembled monolayers to match the surface energy of organic semiconductors for enhancing the OTFT performance. The utility of the hybrid dielectrics for flexible OTFTs was demonstrated by realizing pentacene TFTs on plastic substrates with a low operating voltage at –2.5 V, a high on/off current ratio of 105, a threshold voltage as low as –0.7 V, and a hole mobility up to 0.47 cm2 V−1 s−1, which are comparable to those performed on Si substrates.

Analysis of Subthreshold Swing in Symmetric Junctionless Double Gate MOSFET Using high-k Gate Oxides

Analysis of Subthreshold Swing in Symmetric Junctionless Double Gate MOSFET Using high-k Gate Oxides

Fast Switching of Twisted Nematic Liquid Crystals Display Based on a High-K Yttrium Oxide

Fast Switching of Twisted Nematic Liquid Crystals Display Based on a High-K Yttrium Oxide

Geometric structure and electronic properties of wurtzite GaN/HfO2 interface: A first-principles study

III-V interface with high-k oxide, especially HfO2, is crucial to the development of high mobility microelectronic devices. In this work, we systematically investigated the wurtzite GaN/cubic HfO2 interface based on the first-principles calculations with density functional theory in terms of the geometric structure and electronic properties. In order to mimic the high-k growth conditions, the interfacial oxygen contents in the slab interface models varied to study the interface stability and the relevant electronic structures. It is found that the oxygen rich interface, i.e., oxygen content of 83.3% (O5), shows the most stability in a large range of the oxygen chemical potential from 0 eV to −4.34 eV. Through the calculations of local density of states and Bader charge analysis, we noticed that increasing the interfacial oxygen content leads to the increase of the valence band offset (VBO) and the decrease of the conduction band offset (CBO), respectively. More importantly, interface O5 displays a promising VBO (0.86 eV) and CBO (1.34 eV), which meets the industrial requirements to confine the carrier in the III-V channel materials. Furthermore, no interfacial gap states are observed in interface O5, indicating that O5 is free of Fermi level pinning. This theoretical exploration suggests that varying oxygen content at the interface could result in the optimal interface for the applications of high mobility electronic devices.

Three-dimensional device simulation of random telegraph noise spectroscopy with Coulomb energy variation of the trap in high-k gate oxide

The random telegraph noise (RTN) time constants, capture (τc) and emission (τe) times, have been extensively used to identify the trap position in the gate oxide by comparing the measured τc-over-τe ratio with the Shockley–Read–Hall (SRH) statistics. However, various factors have been shown to affect the accuracy of the extracted trap depth from the SRH-type models, such as three-dimensional (3D) device electrostatics, atomistic doping, metal gate granularity, and Coulomb energy variation (CEV) of the trap. Focusing on CEV in this work, we assume the trap in gate oxide can be regarded as a floating island and then numerically studied the CEV of the trap with 3D drift-diffusion simulation. Analyzing the simulation data, the extracted trap depth without considering CEV in the SRH statistics are quantitatively compared with the data involved CEV.

Determination of the Optimal Sensing Temperature in Pt/Ta₂O₅/MoO₃ Schottky Contacted Nanobelt Straddling Heterojunction.

Nanostructured Schottky barrier gas sensors have emerged as novel semiconductor devices with large surface areas and unique electronic characteristics. Although it is widely known that operating these gas sensors requires heating to an optimal temperature for the highest sensitivity, the fundamental mechanism that governs the temperature-dependent sensitivity has yet been well understood. In this work, we present new evidence to support that thermionic field emission (TFE) is the dominant transport mechanism for Schottky contacted nanostructured heterojunction gas sensors at their optimal sensing temperature. Through the fabrication and characterization of Pt/MoO3 Schottky contacts, and Pt/Ta2O5/MoO3 heterojunctions, we found a previously unreported connection between TFE transport and optimal gas sensing temperature. This connection enables the description of Schottky barrier gas sensing performance using transport theory, which is a major step towards systematic engineering of gas sensors with nanostructured high-k oxide layers.

Structural characterization of tantalum nitride films as wet etch stop layer in advanced multiwork function metal gate MOSFETs

As the dimensions of semiconductor devices become smaller, the use of high-k materials as gate oxides has become necessary for controlling gate leakage current. In addition, to achieve higher performance, conventional polysilicon metal gates have been replaced with multistack metal electrodes with engineered work functions. Thus, a suite of devices with different levels of performance and power usage is available. The integration scheme to create such structures involves an additional deposition step and selective wet etching of titanium nitride (TiN) in a complex patterning scheme following the high-k film deposition. Tantalum nitride (TaN) is one of the candidates used as an etch stop layer in a bilayer scheme of TaN/TiN. This prevents any exposure of high-k hafnium oxide (HfO2) gate oxide to wet etch chemistry in the patterning scheme, which could cause damage and/or skimming, resulting in undesirable effects on device characteristics and reliability. In order to accommodate for shrinking trench widths, these bilayer stacks are kept as thin as possible, which makes monitoring the thickness during various patterning steps very challenging. In this study, the authors present an approach to an offline and inline metrology setup. In order to gain insight into basic layer growth and interdiffusion characteristics, they used x-ray photoelectron spectroscopy and high-resolution transmission electron microscopy. They utilized specular x-ray reflectivity as a first principles method, followed by wavelength dispersive x-ray fluorescence to gain insight into cross-wafer variation on blanket wafers. The results were then fed into models developed for the x-ray photoelectron spectroscopy technique, which can be used as an inline method to characterize the composition and thickness of the patterned wafers for both as-deposited and postetching.

Outstanding memory characteristics with atomic layer deposited Ta2O5/Al2O3/TiO2/Al2O3/Ta2O5 nanocomposite structures as the charge trapping layer

A charge trapping memory device using Ta2O5/Al2O3/TiO2/Al2O3/Ta2O5 (TATiAT) nanocomposite high-k dielectrics as charge trapping layer (CTL) and amorphous Al2O3 as the tunneling and blocking layers has been investigated, in which all the high-k dielectric films were fabricated by atomic layer deposition (ALD) technique. A large memory window of 10.0 V with higher charge trap density of 1.10 × 1013 cm−2 at gate voltage of ±10 V has been achieved. The better storage characteristic is attributed to the inter-diffusion between nanocomposite high-k oxides and the formation of more oxygen vacancies in CTL. The device shows the fast P/E speed and excellent endurance characteristics. A 70% initial memory window can be maintained after 10 years of retention by using the extrapolation method. The large conduction band offsets of 1.02 eV between TATiAT and Al2O3 is beneficial to retention characteristic due to the deep trap level.

Nanoscale Investigation of Defects and Oxidation of HfSe2.

HfSe2 is a very good candidate for a transition metal dichalcogenide-based field-effect transistor owing to its moderate band gap of about 1 eV and its high-κ dielectric native oxide. Unfortunately, the experimentally determined charge carrier mobility is about 3 orders of magnitude lower than the theoretically predicted value. This strong deviation calls for a detailed investigation of the physical and electronic properties of HfSe2. Here, we have studied the structure, density, and density of states of several types of defects that are abundant on the HfSe2 surface using scanning tunneling microscopy and spectroscopy. Compared to MoS2 and WSe2, HfSe2 exhibits similar type of defects, albeit with a substantially higher density of 9 × 1011 cm–2. The most abundant defect is a subsurface defect, which shows up as a dim feature in scanning tunneling microscopy images. These dim dark defects have a substantially larger band gap (1.25 eV) than the pristine surface (1 eV), suggesting a substitution of the Hf atom by another atom. The high density of defects on the HfSe2 surface leads to very low Schottky barrier heights. Conductive atomic force microscopy measurements reveal a very small dependence of the Schottky barrier height on the work function of the metals, suggesting a strong Fermi-level pinning. We attribute the observed Fermi-level pinning (pinning factor ∼0.1) to surface distortions and Se/Hf defects. In addition, we have also studied the HfSe2 surface after the exposure to air by scanning tunneling microscopy and conductive atomic force microscopy. Partly oxidized layers with band gaps of 2 eV and Schottky barrier heights of ∼0.6 eV were readily found on the surface. Our experiments reveal that HfSe2 is very air-sensitive, implying that capping or encapsulating of HfSe2, in order to protect it against oxidation, is a necessity for technological applications.

Low Power Switching Characteristics of CNT Field Effect Transistor Device with Al-Doped ZrHfO2 Gate Dielectric

In this report, we demonstrated a reliable switching effect of carbon nanotube (CNT) field-effect transistor (FET) devices integrated with 99% semiconducting CNT as a channel and high-k oxide as the dielectric. CNT FET devices with high-k oxides of Al-ZrHfO2 and Al2O3 were electrically characterized and compared. There was no considerable hysteresis in the Al2O3-based CNT FET device. The Al-ZrHfO2 with a tetragonal phase-based high dielectric constant (~47), designed by an atomic layer deposition process, showed a reliable switching effect as well as low operation voltage (<±3 V). Charge trapping/detrapping process via oxygen vacancy-related defects of Al-ZrHfO2 was proposed as a primary mechanism to explain a current change of a counterclockwise direction and threshold voltage (Vth) shift for transfer properties. The suggested charge trapping model within bulk oxide was experimentally proven since the hysteresis from the adsorption/desorption of gas molecules to CNT surface was negligible. Endurance characteristics of the CNT switching devices remained stable without any serious current fluctuation during a repetitive cycling test. The memory device with reliable switching properties as well as low operation power would pave a road toward next-generation memory components of portable electronic gadgets.

Rectifying Characteristics of Resonant Tunneling MIS Devices Using Ultra-Thin High-k Oxides Deposited by ALD

The electrical properties of metal–insulator–insulator–insulator–semiconductor nanostructures as rectifiers are investigated. Ultra-thin insulator layers of Al2O3/TiO2/Al2O3 having 2 nm/1 nm/2 nm in thickness are deposited by the atomic layer deposition to enhance resonant tunneling under substrate and gate injection. Superior low-voltage, large-signal, and small-signal nonlinearities such as an asymmetry of 45 at 1 V and a non-linearity of 19 V−1 are obtained.

Thickness-Dependent Electrical Properties of MoS₂ Field-Effect Transistors Fabricated on Sol-Gel Prepared AlOX Layer.

Solution-processed high-k oxide layer, which is typically deposited using atomic layer deposition (ALD), has been proposed and recently demonstrated on molybdenum disulfide (MoS2) field-effect transistors (FETs). In this report, we statistically investigate electrical performance of multilayer MoS2 FETs fabricated on sol-gel AlOX gate-dielectric. More than 10 sample devices with different MoS2 thickness are characterized and compared. For electrical parameters extraction, Y -function method is adopted in order to minimize S/D electrode contact-induced variations. In spite of the relatively rougher surface of the sol-gel AlOX film, no significant difference of electrical performance is observed. The sol-gel prepared AlOX can be considered as a promising high-k gate dielectric for high-performance large-area transistion metal dichalcogenides (TMDs) devices fabrication.

Structural and electrical characterisation of high-k ZrO2 thin films deposited by chemical spray pyrolysis method

As the applicability of high-k oxides in field-effect transistor became enormous, the physical and chemical understanding of their dielectric properties as well as preparation technique should be diligently studied. Herein, we have studied the deposition of zirconium oxide (ZrO2) thin film by chemical spray pyrolysis and we have investigated the influences of deposition temperature (200, 300, 400, 500 °C) and annealing temperature (500, 800 °C) on the morphological, structural, optical, and electrical properties of the film. It was observed that the as-deposited ZrO2 thin films at temperature below 500 °C were smooth, dense, and structurally amorphous – while the ZrO2 thin film deposited at 500 °C are poorly crystalline. As confirmed by Raman and X-ray diffraction peak deconvolution, ZrO2 tetragonal phase was predominant in the film upon annealing at 500 °C, and the monoclinic phase favoured after annealing at 800 °C. As-deposited ZrO2 thin film are optically transparent (above 80% in the visible region) with a slight decrease in transmittance upon annealing at higher temperature. The optical band gap of ZrO2 film was in the range 5.39–5.68 eV and the dielectric constant (k) in the range 4.3–13.0, depending on the deposition temperature.

HfO2/Al2O3 Nanolaminate on Si0.7Ge0.3(100) Surface by Thermal Atomic Layer Deposition

Silicon germanium (SiGe) channels for CMOS are favorable due to high intrinsic carrier mobility and band gap tunability[1] To utilize the superior properties of SiGe, low interface defect density (Dit) must be obtained at the SiGe-high k interface. Germanium oxide (GeOx) is the primary source of interface defects[2]. In comparison with GeOx, SiOx has a higher heat of formation. Using this difference, it is possible to reduce interface defects with selective reduction or diffusion of GeOx by employing an oxygen-scavenging metal as a gate material[4,5] such as aluminum. ALD was performed with TDMAH and H2O to grow 50 cycles (5nm) of HfO2 at 250C. 50 nm thick, 150 um diameter Ni or Al gate metal was deposited by thermal evaporation. C-V measurement were employed to characterized the electronic defects. The interface trap density (Dit) integrated across the band gap was more than an order of magnitude lower for Al vs Ni gated MOSCAPs. From TEM-EELS-EDS measurement, Al gated MOSCAPs were observed to have a very thin interfacial oxide layer (<0.5 nm) with high-k oxide atoms almost directly bonded with the SiGe surface atoms with just a thin SiOx interlyer. Selective scavenging of Ge-O vs Si-O bonds is consistent with a DFT model showing HfO2/SiOx/SiGe interfaces can be defect-free. DFT models also show that two 3- and 5-fold coordinated interfacial Si atoms do not create any mid-gap or band-edge states. These results indicate the need to form a SiOx interface between HfO2 and SiGe, but the same interface may be created with other techniques. The alternative techniques include a selective oxidation of SiGe form SIOx using remote O3 oxidation and ALD of an Si rich layer on SiGe. The key issue is which of the three techniques is manufacturable and can produce both a scale oxide and scaled interlayer. [1] Liu, C. et. al, MRS Bull. 39, 658–662 (2014). [2] Zhang, L. et al, ACS Appl. Mater. Interfaces 8, 19110–19118 (2016). [3] Zhang, L. et al, ACS Appl. Mater. Interfaces 7, 20499–20506 (2015). [4] Kim, H. et al, J. Appl. Phys. 96, 3467–3472 (2004). [5] Frank, M. et al, ECS Solid State Lett. 2, N8–N10 (2012). [6] Sardashti, K. et al. Appl. Surf. Sci. 366, 455–463 (2016)

Thermal property engineering of InSe layer by a thin Al2O3 stress liner

We investigate the thermal properties of thin InSe layers with high-κ oxide Al2O3 stress liners. Temperature-dependent Raman spectroscopy demonstrated that the Al2O3 passivation layer significantly reduced the thermal variation coefficients of the in-plane E2g1 phonon mode of the InSe layer from −0.03284 cm−1/K to −0.0212 cm−1/K in comparison with the InSe sample without the Al2O3 capping layer. Combined with power-dependent Raman spectroscopy, the in-plane thermal conductivity of InSe reaches about 53.1 W/mK, ∼40% greater than that without the Al2O3 capping layer, 38.2 W/mK, which is attributed to the large thermal conductivity of Al2O3 and the electron-phonon interactions at the interface. Generally, this work will contribute to improving the performances of the InSe-based nano-devices and extending their applications profoundly.

Resonant tunneling MIIIS diode based on intrinsic quantum-well formation of ultra-thin atomic layered films after band-offset engineering

Negative Differential Resistance (NDR) is obtained at room temperature for Metal-Insulator-Insulator-Insulator-Semiconductor (MIIIS) diodes after band offset engineering. After post-metallization annealing (PMA), this characteristic is lost due to an inner diffusion of elements. The MIIIS diodes (as-prepared and PMA) were fabricated using a gate stack of atomic-layer deposited ultra-thin (2 nm/1 nm/2 nm) high-k oxides (Al2O3/HfO2/Al2O3) and their I-V, C-V and I-V-T characteristics were studied. A quantum well of 1.3 eV is obtained in the intermediate oxide for the as-prepared sample, promoting quantization of energy levels and resulting in three NDR zones at 0.1, 0.28 and 0.5 V due to the effects of resonant tunneling (RT). These zones are non-existent in the PMA diode. RT was found to be dominant at low voltages due to the discrete energy levels at the conduction band of the HfO2 oxide. After RT, the main conduction mechanism for both diodes is Poole-Frenkel.

Solution Processed Metal Oxide High-κ Dielectrics for Emerging Transistors and Circuits.

The electronic functionalities of metal oxides comprise conductors, semiconductors, and insulators. Metal oxides have attracted great interest for construction of large-area electronics, particularly thin-film transistors (TFTs), for their high optical transparency, excellent chemical and thermal stability, and mechanical tolerance. High-permittivity (κ) oxide dielectrics are a key component for achieving low-voltage and high-performance TFTs. With the expanding integration of complementary metal oxide semiconductor transistors, the replacement of SiO2 with high-κ oxide dielectrics has become urgently required, because their provided thicker layers suppress quantum mechanical tunneling. Toward low-cost devices, tremendous efforts have been devoted to vacuum-free, solution processable fabrication, such as spin coating, spray pyrolysis, and printing techniques. This review focuses on recent progress in solution processed high-κ oxide dielectrics and their applications to emerging TFTs. First, the history, basics, theories, and leakage current mechanisms of high-κ oxide dielectrics are presented, and the underlying mechanism for mobility enhancement over conventional SiO2 is outlined. Recent achievements of solution-processed high-κ oxide materials and their applications in TFTs are summarized and traditional coating methods and emerging printing techniques are introduced. Finally, low temperature approaches, e.g., ecofriendly water-induced, self-combustion reaction, and energy-assisted post treatments, for the realization of flexible electronics and circuits are discussed.

An Overview of High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Capacitors and Field-Effect Transistors

Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high-k oxides on hydrogenated-diamond (H-diamond) for metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High-k oxide insulators are deposited using atomic layer deposition (ALD) and sputtering deposition (SD) techniques. Electrical properties of the H-diamond MOS capacitors with high-k oxides of ALD-Al2O3, ALD-HfO2, ALD-HfO2/ALD-Al2O3 multilayer, SD-HfO2/ALD-HfO2 bilayer, SD-TiO2/ALD-Al2O3 bilayer, and ALD-TiO2/ALD-Al2O3 bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the ALD-Al2O3/H-diamond and SD-HfO2/ALD-HfO2/H-diamond MOS capacitors. The k value of 27.2 for the ALD-TiO2/ALD-Al2O3 bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p-type channel characteristics for the ALD-Al2O3/H-diamond, SD-HfO2/ALD-HfO2/H-diamond, and ALD-TiO2/ALD-Al2O3/H-diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high-k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFET gas sensors.