High-k Oxide Research Articles

Density and Capture Cross-Section of Interface Traps in GeSnO2 and GeO2 Grown on Heteroepitaxial GeSn.

An imperative factor in adapting GeSn as the channel material in CMOS technology, is the gate-oxide stack. The performance of GeSn transistors is degraded due to the high density of traps at the oxide-semiconductor interface. Several oxide-gate stacks have been pursued, and a midgap Dit obtained using the ac conductance method, is found in literature. However, a detailed signature of oxide traps like capture cross-section, donor/acceptor behavior and profile in the bandgap, is not yet available. We investigate the transition region between stoichiometric insulators and strained GeSn epitaxially grown on virtual Ge substrates. Al2O3 is used as high-κ oxide and either Ge1-xSnxO2 or GeO2 as interfacial layer oxide. The interface trap density (Dit) profile in the lower half of the bandgap is measured using deep level transient spectroscopy, and the importance of this technique for small bandgap materials like GeSn, is explained. Our results provide evidence for two conclusions. First, an interface traps density of 1.7 × 10(13) cm(-2)eV(-1) close to the valence band edge (Ev + 0.024 eV) and a capture cross-section (σp) of 1.7 × 10(-18) cm(2) is revealed for GeSnO2. These traps are associated with donor states. Second, it is shown that interfacial layer passivation of GeSn using GeO2 reduces the Dit by 1 order of magnitude (2.6 × 10(12) cm(-2)eV(-1)), in comparison to GeSnO2. The results are cross-verified using conductance method and saturation photovoltage technique. The Dit difference is associated with the presence of oxidized (Sn(4+)) and elemental Sn in the interfacial layer oxide.

Demonstration of large field effect in topological insulator films via a high-κ back gate

The spintronics applications long anticipated for topological insulators (TIs) has been hampered due to the presence of high density intrinsic defects in the bulk states. In this work we demonstrate the back-gating effect on TIs by integrating Bi2Se3 films 6–10 quintuple layer (QL) thick with amorphous high-κ oxides of Al2O3 and Y2O3. Large gating effect of tuning the Fermi level EF to very close to the band gap was observed, with an applied bias of an order of magnitude smaller than those of the SiO2 back gate, and the modulation of film resistance can reach as high as 1200%. The dependence of the gating effect on the TI film thickness was investigated, and ΔN2D/ΔVg varies with TI film thickness as ∼t−0.75. To enhance the gating effect, a Y2O3 layer thickness 4 nm was inserted into Al2O3 gate stack to increase the total κ value to 13.2. A 1.4 times stronger gating effect is observed, and the increment of induced carrier numbers is in good agreement with additional charges accumulated in the higher κ oxides. Moreover, we have reduced the intrinsic carrier concentration in the TI film by doping Te to Bi2Se3 to form Bi2TexSe1−x. The observation of a mixed state of ambipolar field that both electrons and holes are present indicates that we have tuned the EF very close to the Dirac Point. These results have demonstrated that our capability of gating TIs with high-κ back gate to pave the way to spin devices of tunable EF for dissipationless spintronics based on well-established semiconductor technology.

Low Leakage Current Al2O3 Metal-Insulator-Metal Capacitors Formed By Atomic Layer Deposition at Optimized Process Temperature and O2 Post Deposition Annealing

High-k oxide material with a high capacitance density, low leakage current density, high-dielectric breakdown voltage and small quadruple voltage coefficient of the capacitance is important for on-chip metal-insulator-metal (MIM) capacitors as well as gate insulators for semiconductor power devices. So in order to improve the quality of such films, a post-deposition process, such as annealing is expected to be effective. In this paper, we carried out various annealing steps after deposition of Al2O3 films with thermal ALD. The electrical characteristics of these Al2O3 films were evaluated. Annealing was proven to be effective in improving the Al2O3 film quality decrease the leakage current and the fixed charge. For O2 annealing at 400°C of MIM capacitor structures containing Al2O3 films deposited with thermal ALD using H2O at a relatively low temperature of 75°C. We achieved a leakage current density of 10-9A/cm2 level and a capacitance density above 10fF/μm2. However, it it is necessary to improve the voltage dependence of the capacitance. For future optimization not only the post-deposition process should be investigated but also the ALD deposition itself, including the selection of the oxidizing co-reactant.

Features of carrier tunneling between the silicon valence band and metal in devices based on the Al/high-K oxide/SiO2/Si structure

The features of electron tunneling from or into the silicon valence band in a metal–insulator–semiconductor system with the HfO2(ZrO2)/SiO2 double-layer insulator are theoretically analyzed for different modes. It is demonstrated that the valence-band current plays a less important role in structures with HfO2(ZrO2)/SiO2 than in structures containing only silicon dioxide. In the case of a very wide-gap high-K oxide ZrO2, nonmonotonic behavior related to tunneling through the upper barrier is predicted for the valence-band–metal current component. The use of an insulator stack can offer certain advantages for some devices, including diodes, bipolar tunnel-emitter transistors, and resonant-tunneling diodes, along with the traditional use of high-K insulators in a field-effect transistor.

RT Atomic Layer Deposition of ZrO2 By Using Plasma Excited Water Vapor

Size of semiconductor devices in large-scale integration has reached the submicron range where gate oxide films in metal oxide semiconductor (MOS) devices need to be fabricated at a nanometer scale. Atomic layer deposition (ALD) is a technology for depositing dielectric films with monolayer precision by repeating adsorption of a source gas on substrate that is subsequently reactivated for further adsorption [1]. Zirconium oxide (ZrO2) is believed to be a candidate as the high-k gate oxide material [2]. The growth temperature for the ZrO2 deposition has been desired to be decreased to near room temperature (RT) because the interfacial layer is formed by the solid phase reaction with heating process [3]. In this work, we developed a RT atomic layer deposition of ZrO2 with tetrakis (ethylmethylamino) zirconium (TEMAZ) and a remote-plasma excited water vapor.A p-type Si(100) substrate with a resistivity of 8-12 Ωcm was used as a sample. Prior to the experiment, the sample was cleaned with a buffered HF acid solution and sulfuric acid-hydrogen peroxide mixture. TEMAZ as the zirconium precursor was introduced with a variable leak valve. An induction plasma system generating oxidizing gas was installed to the ALD chamber as shown in Fig.1. The source gas for the oxidizing gas is a mixture of H2O vapor and Ar gas. The plasma was generated in a glass tube with an induction coil with a frequency of 13.56MHz and a RF power of 30 W. Before the ALD process, the substrate surface was treated with the plasma excited water vapor for 5 min to be terminated with OH groups. For the ZrO2 deposition, we repeated the cycle of TEMAZ saturation and the oxidizing gas treatment at RT. The TEMAZ exposure was set to 1.12×10-3 Torr×100 s. The saturation of TEMAZ on the hydroxylated surface has been confirmed by the IR absorption spectroscopy. The plasma excited oxidizing gas was injected for 150 s. The oxidization state of the ZrO2 film was evaluated by X-ray photoelectron spectroscopy (XPS). The thickness of the grown film was measured by spectroscopic ellipsometry.Fig.2 shows Zr3d spectra obtained from ZrO2 on Si grown by the present ALD. According to the increase in the ALD cycles, the Zr3d5/2 peak at around 181.9 eV evolves. The peak position indicates the full oxidized ZrO2 growth on Si [4]. Fig.3 shows the ZrO2 thickness as a function of the ALD cycle. The linear increase of ZrO2 thickness with the ALD cycle indicates that the ZrO2 is grown in the ALD mode. The growth rate is estimated to be 0.14 nm/cycle. This value is comparable with those released in the conventional thermal ALD studies [5].To conclude, we developed the non-heating, RT ALD of ZrO2 with the plasma enhanced technology. We are now investigating the electrical characteristics of ZrO2 MOS on Si and Ge, which will be released elsewhere. The RT grown ZrO2 films might be also applicable for the anticorrosion coatings on plastic material. In the conference, we present not only the details of growth experiment but also discuss the growth kinetics of RT ALD.Acknowledgement This work was partly supported by JST-CREST. We would like to express the deepest appreciation to AIR-LIQUIDE for the high quality precursor of TEMAZ.

Rapid Thermal Annealing in MgO Sensing EIS Membrane for Bio-Sensor Applications

We tried to find an alternative dielectric film to own the high quality sensitive properties, so that, magnesium oxide (MgO) has been selected as a pH sensitive dielectric for the EIS operation, and is known as an alternative gate dielectric as CMOS technology has aggressively scaled down.The high-k MgO as sensing membrane on EIS structure and to investigated the characteristics of the different rapid thermal annealing(RTA) temperature in oxygen ambient. Furthermore, we studied the sensing performance of the MgO EIS structure tested in different ion (H+,Na+, K+, Urea, Glucose) solution. The electrolyte-insulator-semiconductor (EIS) structures with MgO sensing membranes were fabricated on 4-inch n-type (100) Si wafer, which have a resistivity of 5–10 Ω-cm. Before deposition of the MgO film, the wafers were cleaned by using HF-dip (HF: H2O = 1:100) to remove the native oxide. Then, a 50-nm MgO was deposited by radio frequency (RF) reactive sputtering on n-type silicon wafer. During RF sputtering, Mg oxide-target was used with 25 sccm argon flow rate (Ar: O2=25:0). The (RF) power and pressure are 150Watt and 20mTorr, respectively. Next, Samples was annealed at different temperatures (600oC, 700oC, 800oC) by rapid thermal annealing (RTA) in O2 ambient for 30 sec. The back-side contact of the Si wafer was deposited by Al film with 300nm-thick. Then, sensing area was defined by standard photolithography process using a photosensitive epoxy, SU8-2005 of MicroChem Inc. Finally, the samples were fabricated on the copper lines of printed circuit board (PCB) by silver gel. Epoxy package was used to separate the EIS structure and the copper line. In this study, we report an electrolyte–insulator–semiconductor (EIS) sensor with a high-k magnesium oxide (MgO) as sensing material. The effect of rapid thermal annealing (RTA) on the deposited sensing membrane has been studied in terms of structural and sensing characteristics. We used X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), and atomic force microscopy (AFM) to investigate the structural and morphological characteristics of deposited films. Furthermore, we studied the sensing performance of the MgO EIS structure in different ion solutions such as Urea and Glucose solutions. EIS device with MgO as sensing membrane that has been subjected to 800 ºC RTA treatment exhibits better sensing characteristics such as sensitivity of 61.64 mV/pH, hysteresis voltage of 5.03mV and 1.55mV/hr drift rate.

High-k Dielectric Passivation for GaN Diode with a Field Plate Termination

Vertical structured Gallium nitride (GaN) p-n junction diodes with improved breakdown properties have been demonstrated using high-k dielectric passivation underneath the field plate. Simulation results at a reverse voltage of 1 kV showed that the maximum electric field near the mesa-etched p-n junction edges covered with film of dielectric constant k = 10 was reduced to 2.0 MV/cm from 3.0 MV/cm (SiO2 (k = 3.9)). The diodes were fabricated using the high-k mixed oxide of SiO2 and CeO2 with k = 12.3. I–V characteristics of the diode with a field plate showed a breakdown voltage above 2 kV with an increased avalanche resistance. This means that the electric field reduces at the periphery of the mesa-etched p-n junction and is uniformly formed across the whole p-n junction. It is clear that high-k dielectric film passivation and filed plate termination are essential techniques for GaN power devices.

ZrO2 and HfO2 dielectrics on (001) n-InAs with atomic-layer-deposited in situ surface treatment

The electrical properties of ZrO2 and HfO2 gate dielectrics on n-InAs were evaluated. Particularly, an in situ surface treatment method including cyclic nitrogen plasma and trimethylaluminum pulses was used to improve the quality of the high-κ oxides. The quality of the InAs-oxide interface was evaluated with a full equivalent circuit model developed for narrow band gap metal-oxide-semiconductor (MOS) capacitors. Capacitance–voltage (C–V) measurements exhibit a total trap density profile with a minimum of 1 × 1012 cm−2 eV−1 and 4 × 1012 cm−2 eV−1 for ZrO2 and HfO2, respectively, both of which are comparable to the best values reported for high-κ/III-V devices. Our simulations showed that the measured capacitance is to a large extent affected by the border trap response suggesting a very low density of interface traps. Charge trapping in MOS structures was also investigated using the hysteresis in the C–V measurements. The experimental results demonstrated that the magnitude of the hysteresis increases with increase in accumulation voltage, indicating an increase in the charge trapping response.

The temperature dependence on the electrical properties of dysprosium oxide deposited on n-porous GaAs

This paper describes the electrical and dielectric characteristics for the first time of the high-k Dy2O3 oxide film deposited on the porous GaAs substrate by electron beam deposition under ultra vacuum. Morphological characterization is investigated by atomic force microscopy (AFM). The electrical and dielectric properties of Co/Au/Dy2O3/n-porous GaAs structure were studied in the temperature range of 80–500 K. The conductance and capacitance measurements were performed as a function of bias voltage and frequency. The dielectric constant (ε′), dielectric loss (ε″) and dielectric loss tangent (tanδ) of the structure are obtained from capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements. These parameters are found to be strong functions of temperature and bias voltage. In the forward bias region, C–V plots show a negative capacitance (NC) behavior, ε′–V plots for each temperature value take negative values as well. Such negative values of C correspond to the maximum of the conductance (G/ω). The negative capacitance values appear abnormal when compared to the conventional behavior of ideal Schottky barrier diode (SBD) and metal–oxide–semiconductor (MOS) structures. The following behavior of the C and ε′ in the forward bias region has been explained with the minority-carrier injection and relaxation theory. From DC conductance study, electronic conduction is found to be dominated by thermally activated hopping at high temperature. Activation energy is deduced from the variation of conductance with temperature. The Nyquist plots exhibited single semi-circular arcs which were well fitted to an equivalent circuit.

Photo-patternable high-k ZrOx dielectrics prepared using zirconium acrylate for low-voltage-operating organic complementary inverters

Solution-processed dielectric materials with a high dielectric constant (k) have attracted considerable attention due to their potential applications in low-voltage-operating organic field-effect transistors (OFETs) for realizing large-area and low-power electronic devices. In terms of device commercialization, the patterning of each film component via a facile route is an important issue. In this study, we introduce a photo-patternable precursor, zirconium acrylate (ZrA), to fabricate photo-patterned high-k zirconium oxide (ZrOx) dielectric layers with UV light. Solution-processed ZrA films were effectively micro-patterned with UV exposure and developing, and transitioned to ZrOx through a sol-gel reaction during deep-UV annealing. The UV-assisted and ∼10 nm-thick ZrOx dielectric films exhibited a high capacitance (917.13 nF/cm2 at 1 KHz) and low leakage current density (10−7 A/cm2 at 1.94 MV/cm). Those films could be utilized as gate dielectric layers of OFETs after surface modification with ultrathin cyclic olefin copolymer layers. Finally, we successfully fabricated organic complementary inverters exhibiting hysteresis-free operation and high voltage gains of over 42 at low voltages of ≤3 V.

Origin of Indium Diffusion in High-k Oxide HfO2.

Indium (In) out-diffusion through high-k oxides severely undermines the thermal reliability of the next generation device of III-V/high-k based metal oxide semiconductor (MOS). To date, the microscopic mechanism of In diffusion is not yet fully understood. Here, we utilize angle resolved X-ray photoelectron spectroscopy (ARXPS) and density functional theory (DFT) to explore In diffusion in high-k oxide HfO2. Our ARXPS results confirm the In diffusion through as-prepared and annealed HfO2 grown on InP substrate. The theoretical results show that the In diffusion barrier is reduced to ∼0.88 eV in the presence of oxygen vacancies (VO), whereas this barrier is as high as ∼4.78 eV in pristine HfO2. Fundamentally, we found that the high feasibility of In diffusion is owing to In nonbonding with its neighboring atoms. These findings can be extended to understand the In diffusion in other materials in addition to HfO2.

Positive and negative dipole layer formation at high-k/SiO2 interfaces simulated by classical molecular dynamics

We show the electric dipole layer formed at a high-k/SiO2 interface can be explained by the imbalance between the migration of oxygen ions and metal cations across the high-k/SiO2 interface. Classical molecular dynamics (MD) simulations are performed for Al2O3/SiO2, MgO/SiO2, and SrO/SiO2 interfaces. The simulations qualitatively reproduce the experimentally observed flatband voltage (VFB) shifts of these systems. In the case of the Al2O3/SiO2 interface, a dipole layer is formed by the migration of oxygen ions from the Al2O3 side to the SiO2 side. By way of contrast, opposite dipole moments appear at the MgO/SiO2 and SrO/SiO2 interfaces, because of a preferential migration of metal cations from the high-k oxide toward the SiO2 layer in the course of the formation of a stable silicate phase. These results indicate that the migrations of both oxygen ions and metal cations are responsible for the formation of the dipole layer in high-k/SiO2 interfaces.

Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs

In this paper, the graded channel gate stack (GCGS) DG MOSFET structure is studied in view of increasing device performance and immunity to short channel effects. The device has the advantage of improved gate oxide reliability, suppressed parasitic bipolar effect, lower DIBL and higher cut-off frequency. Therefore, the device must be investigated with respect to the variation of different structure dependent parameters before fabrication to have better reliability and constancy. In this work we have studied the device with respect to variation in high K oxide thickness (toxh) and channel length (Lg) to have better understanding on variation of different analog/RF performance parameters. The results validate that variations in toxh of the device significantly alters device performance parameters and must be pre accounted for realizing reliable analog/RF system on chip circuits.

Swift ion irradiation effect on high-k ZrO2- and Al2O3-based MOS devices

ABSTRACTThis paper describes the heavy ion-induced effects on the electrical characteristics of reactively sputtered ZrO2 and Al2O3 high-k gate oxides deposited in argon plus nitrogen containing plasma. Radiation-induced degradation of sputtered high-k dielectric ZrO2/Si and Al2O3/Si interface was studied using 45 MeV Li3+ ions. The devices were irradiated with Li3+ ions at various fluences ranging from 5 × 109 to 5 × 1012 ions/cm2. Capacitance–voltage and current–voltage characteristics were used for electrical characterization. Shift in flat band voltage towards negative value was observed in devices after exposure to ion radiation. Post-deposition annealing effect on the electrical behavior of high-k/Si interface was also investigated. The annealed devices showed better electrical and reliability characteristics. Different device parameters such as flat band voltage, leakage current, interface defect density and oxide-trapped charge have been extracted.The surface morphology and roughness values for films deposited in nitrogen containing plasma before and after ion radiation are extracted from Atomic Force Microscopy.

Guest Editorial IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

The papers in this special section focus on the technology and applications supported by defect/fault tolerance in very large scale integration and nanotechnology systems. With increasing demand for ever smaller, portable, energy-efficient, and high-performance electronic systems, scaling of CMOS technology continues. As CMOS scaling approaches physical limits, continued innovation in materials, manufacturing processes, device structures, and design paradigms have been necessary. High-κ oxide and metal-gate stack were introduced to address oxide leakage; thin body undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage; restricted design rules were introduced to improve layout efficiency; yet CMOS technology continues to be challenged in the areas of device aging and reliability. While CMOS is expected to be the dominant semiconductor technology for the foreseeable future—due to for reasons that are both technological and financial, alternatives to CMOS technology are attracting attention from the researchers.

Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

The papers in this special issue focus on defect and fault tolerance in VLSI and nanotechnology systems. With the increasing demand for ever smaller, portable, energy-efficient and high-performance electronic systems, scaling of CMOS technology continues. As CMOS scaling approaches physical limits, continued innovation in materials, manufacturing processes, device structures and design paradigms have been necessary. High-k oxide and metal-gate stack were introduced to address oxide leakage; thin body undoped channels, and multiple-gate structures were introduced to mitigate subthreshold leakage; restricted design rules were introduced to improve layout efficiency; yet CMOS technology continues to be challenged in the areas of device aging and reliability. While CMOS is expected to be the dominant semiconductor technology for the foreseeable future, for reasons that are both technological and financial, alternatives to CMOS technology are attracting attention from the researchers.

Triangular Gate-all-around Nanowire FETs with Enhanced Electrical Performance using High-K Dielectric Gate Oxide

Triangular Gate-all-around Nanowire FETs with Enhanced Electrical Performance using High-K Dielectric Gate Oxide

A Low-Leakage Epitaxial High-κ Gate Oxide for Germanium Metal-Oxide-Semiconductor Devices.

Germanium (Ge)-based metal-oxide-semiconductor field-effect transistors are a promising candidate for high performance, low power electronics at the 7 nm technology node and beyond. However, the availability of high quality gate oxide/Ge interfaces that provide low leakage current density and equivalent oxide thickness (EOT), robust scalability, and acceptable interface state density (D(it)) has emerged as one of the most challenging hurdles in the development of such devices. Here we demonstrate and present detailed electrical characterization of a high-κ epitaxial oxide gate stack based on crystalline SrHfO3 grown on Ge (001) by atomic layer deposition. Metal-oxide-Ge capacitor structures show extremely low gate leakage, small and scalable EOT, and good and reducible D(it). Detailed growth strategies and postgrowth annealing schemes are demonstrated to reduce Dit. The physical mechanisms behind these phenomena are studied and suggest approaches for further reduction of D(it).

Thermally stable yttrium–scandium oxide high-k dielectrics deposited by a solution process

We investigated the thermal stability of electrical properties in ternary alloy (YxSc1−x)2O3 high-k oxides as a function of yttrium fraction, x. The yttrium–scandium oxide dielectric films are deposited using a facile ink-based process. The oxides have a stoichiometry-dependent relative dielectric constant of 26.0 to 7.7 at 100 kHz, low leakage current density of 10−8 A·cm−2, high breakdown field of 4 MV⋅cm−1, and interface trap density of 1012 cm−2·eV−1 with silicon. Compared with binary oxides, ternary alloys exhibit less frequency dispersion of the dielectric constant and a higher crystallization temperature. After crystallization is induced through a 900 °C anneal, ternary (Y0.6Sc0.4)2O3 films maintain their low leakage current and high breakdown field. In contrast, the electrical performance of the binary oxides significantly degrades following the same treatment. The solution-processed ternary oxide dielectrics demonstrated here may be used as high-k gate insulators in complementary metal-oxide semiconductor (CMOS) technologies, in novel electronic material systems and devices, and in printed, flexible thin film electronics, and as passivation layers for high power devices. These oxides may also be used as insulators in fabrication process flows that require a high thermal budget.

Band offsets and electronic structures of interface between In0.5Ga0.5As and InP

III–V semiconductor interfacing with high-κ gate oxide is crucial for the high mobility metal-oxide-semiconductor field transistor device. With density functional theory calculations, we explored the band offsets and electronic structures of the In0.5Ga0.5As/InP interfaces with various interfacial bondings. Among six different bonding interfaces, we found that P-In(Ga) bonding interface showed the highest stability. Local density of states calculations was adopted to calculate the band offsets. Except for the metallic interface, we noticed that neither valence band offset nor conduction band offset depended on the interfacial bondings. For the most stable P-In(Ga) interface, we did not observe any gap states. Furthermore, we explored the P-In(Ga) interfaces with interfacial P-As exchange defects, which slightly modified the interface stability and the band offsets but did not produce any gap states. These findings provide solid evidence that InP could serve as a promising interfacial passivation layer between III–V material and high-κ oxide in the application of high mobility devices.