High-k Oxide Research Articles

Multifunctional Hybrid Multilayer Gate Dielectrics with Tunable Surface Energy for Ultralow-Power Organic and Amorphous Oxide Thin-Film Transistors.

For large-area, printable, and flexible electronic applications using advanced semiconductors, novel dielectric materials with excellent capacitance, insulating property, thermal stability, and mechanical flexibility need to be developed to achieve high-performance, ultralow-voltage operation of thin-film transistors (TFTs). In this work, we first report on the facile fabrication of multifunctional hybrid multilayer gate dielectrics with tunable surface energy via a low-temperature solution-process to produce ultralow-voltage organic and amorphous oxide TFTs. The hybrid multilayer dielectric materials are constructed by iteratively stacking bifunctional phosphonic acid-based self-assembled monolayers combined with ultrathin high-k oxide layers. The nanoscopic thickness-controllable hybrid dielectrics exhibit the superior capacitance (up to 970 nF/cm2), insulating property (leakage current densities <10-7 A/cm2), and thermal stability (up to 300 °C) as well as smooth surfaces (root-mean-square roughness <0.35 nm). In addition, the surface energy of the hybrid multilayer dielectrics are easily changed by switching between mono- and bifunctional phosphonic acid-based self-assembled monolayers for compatible fabrication with both organic and amorphous oxide semiconductors. Consequently, the hybrid multilayer dielectrics integrated into TFTs reveal their excellent dielectric functions to achieve high-performance, ultralow-voltage operation (< ± 2 V) for both organic and amorphous oxide TFTs. Because of the easily tunable surface energy, the multifunctional hybrid multilayer dielectrics can also be adapted for various organic and inorganic semiconductors, and metal gates in other device configurations, thus allowing diverse advanced electronic applications including ultralow-power and large-area electronic devices.

Poly(oligo(ethylene glycol) methyl ether methacrylate) Brushes on High-κ Metal Oxide Dielectric Surfaces for Bioelectrical Environments.

Advances in electronics and life sciences have generated interest in "lab-on-a-chip" systems utilizing complementary metal oxide semiconductor (CMOS) circuitry for low-power, portable, and cost-effective biosensing platforms. Here, we present a simple and reliable approach for coating "high-κ" metal oxide dielectric materials with "non-fouling" (protein- and cell-resistant) poly(oligo(ethylene glycol) methyl ether methacrylate (POEGMA) polymer brushes as biointerfacial coatings to improve their relevance for biosensing applications utilizing advanced electronic components. By using a surface-initiated "grafting from" strategy, POEGMA films were reliably grown on each material, as confirmed by ellipsometric measurements and X-ray photoelectron spectroscopy (XPS) analysis. The electrical behavior of these POEGMA films was also studied to determine the potential impact on surrounding electronic devices, yielding information on relative permittivity and breakdown field for POEGMA in both dry and hydrated states. We show that the incorporation of POEGMA coatings significantly reduced levels of nonspecific protein adsorption compared to uncoated high-κ dielectric oxide surfaces as shown by protein resistance assays. These attributes, combined with the robust dielectric properties of POEGMA brushes on high-κ surfaces open the way to incorporate this protein and cell resistant polymer interface into CMOS devices for biomolecular detection in a complex liquid milieu.

Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low-k). To supplement low-k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high-k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high-k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3.

High-k oxides by atomic layer deposition—Applications in biology and medicine

Wide band gap oxides grown by atomic layer deposition (ALD) are intensively studied for applications as insulators (gate oxides in field effect transistors) and as resistance switching materials in electronic memories. For these applications, compositions of dielectric films (laminar structures of HfO2, TiO2, ZrO2, and Al2O3) can also be used. Our research shows that the same layers show antibacterial activity comparable to ZnO. For mentioned application, it is important that the ALD allows uniform coating of various materials, including temperature sensitive ones (e.g., perishable fabrics) and equipment and instruments (including implants) used in hospitals and in a food industry. Here, the authors present the antibacterial activity of ALD-deposited metal oxides, promising a range of potential applications in medicine, veterinary, broader health care, and food industry.

Universal conformal ultrathin dielectrics on epitaxial graphene enabled by a graphene oxide seed layer

The amphiphilic nature of graphene oxide (GO) is exploited as a seed layer to facilitate the ultrathin and conformal high-κ metal oxide (MOX) deposition on defect-free epitaxial graphene (EG) by atomic layer deposition (ALD). Three different high-κ metal oxides (Al2O3, HfO2 and TiO2) with various thicknesses (4–20 nm) were grown on ultrathin (1.5 nm) GO seed layers on EG. The quality of such dielectrics was examined by fabricating various metal-insulator-graphene (MIG) type devices. For MIG tunnel devices, on-off ratios of 104 and 103 were obtained for 4 nm Al2O3 and HfO2 dielectric layers, respectively. Additionally, no defect/trap assisted conduction behavior was observed. Graphene field effect transistors (GFETs) with bi-layer metal oxide stack (6 nm TiO2/14 nm HfO2) demonstrated a peak on-state current of 0.16 A/mm, an on-resistance of 6.8 Ω mm, an Ion/Ioff ratio of ∼4, and a gate leakage current below 10 pA/mm at Vds = 1 V and Vgs = 4 V. Capacitance-voltage measurement of the same GFETs exhibited a low hysteresis and nearly ideal dielectric constants. These results demonstrate a simple yet cost-effective universal way of wafer-scale ultrathin high-κ dielectrics deposition on epitaxial graphene by ALD.

Charge density at the Al-=SUB=-2-=/SUB=-O-=SUB=-3-=/SUB=-/Si interface in Metal-Insulator-Semiconductor devices: semiclassical and quantum mechanical descriptions

In this paper, a quantum correction computation of the inversion layer of charge density was investigated. This study is carried out for a one-dimensional Metal-Insulator-Semiconductor (MIS) structure with (100) oriented P-type silicon as substrate. The purpose of this paper is to point out the differences between the semiclassical and quantum-mechanical charge description at the interface Al2O3/Si, and to identify some electronic properties of our MIS device using different thickness of the high-k oxide and diverse temperature with different carrier statitics (Fermi--Dirak statitics and Boltzmann statitics). In particular, the calculations of capacitance voltage (C-V), sheet electron density, a relative position of subband energies and their wave functions are performed to examine qualitatively and quantitatively the electron states and charging mechanisms in our device. DOI: 10.21883/FTP.2017.12.45185.8190

Development of all-solution-processed nanocrystal memory

We developed an all-solution-processed nanocrystal memory containing high density (∼1 × 1012 particles·cm−2) Au-SiO2 core-shell nanoparticles (NPs) within a uniform HfO2 matrix. High-quality HfO2 high-κ oxide composed of ultra-thin (<10 nm) tunnel and control oxide layers were prepared on a silicon substrate by the spin-on sol-gel process. The Au-SiO2 core-shell nanocomposite was also constructed by solution process using 3-aminopropyltrimethoxysilane (APTMS) as a functional mediator. This APTMS provides dual functions: (1) to serve as a binder for catching colloidal Au NPs onto the HfO2 substrate, and (2) to form a protective layer to cover up the Au NP core. The APTMS shell layer was well controlled through the self-assembly monolayer (SAM) layer-by-layer process with a self-limiting feature. It thermally decomposed into sub-nano thick SiO2 shell by post-deposition annealing, playing a key role in surmounting the deficiency of HfO2 for the use of both the tunnel oxide and the control oxide in the nanocrystal memory. This approach efficiently improved the application of a crystalline HfO2 nano-film for electronic device. By elaborately integrating the solution processes of the HfO2 oxide layer and the Au-SiO2 core-shell NPs, a high-performance nanocrystal memory was obtained. This study demonstrated the potential of chemical solution process for nanofabrication application.

Memory and negative-resistance effects in a strained metal-gate high-k n-type field-effect-transistor from 375 K down to 77 K

We introduce an experimental alternative way of looking into the charging and discharging mechanism inside a high-k stacked oxide of a metal-gate strained n-type Field-Effect-Transistor (nFET). This alternative way reproduces a memory and negative resistance effect by biasing the nFET device in a non-conventional way. This is achieved by forward-biasing the drain-bulk junction and by setting the gate electrode in a high-impedance mode. The produced negative resistance effect (NRE) has a controllable peak-to-valley current ratio (PVCR) that goes from about 3.0 up to a value of 5.5 at room temperature. The PVCR increases up to 8.35 at T = 225 K and reduces to 2.84 at T = 375 K in a linear trend. The memory effect is observed when the drain-bulk junction voltage is swept from low to high values and back from high to low values. From low to high forward drain-bulk bias the NRE shows up and vanishes when coming back from high to low forward drain-bulk bias. The NRE and memory effects are attributed to a coupled-gate oxide charging/discharging mechanism with an induced bipolar transistor action in the channel of the FET.

Simulation of Electron Transmittance and Tunneling Current in a Metal-Oxide- Semiconductor Capacitor with a High-K Dielectric Stack of HfO2 and SiO2 Using Exponential- and Airy-Wavefunction Approaches and a Transfer Matrix Method

Analytical expressions of electron transmittance and tunneling current in a metal-oxide-semiconductor (MOS) capacitor with a high dielectric constant (high-K) oxide stack of HfO2 and SiO2 and a negative bias applied to the metal gate were derived. Exponential- and Airy-wavefunction approaches were employed in deriving analytically the electron transmittance and tunneling current. A numerical approach based on a transfer matrix method was used as a standard to evaluate the analytical approaches. It was found that the transmittances obtained under the exponential- and Airy-wavefunction approaches and the TMM are matching for low electron energies, while for higher energies only the transmittances calculated by employing the Airy- wavefunction approach is the same as those computed by using the TMM. It was also found that the tunneling currents calculated by using the exponential- and the Airy-wavefunction approaches and the TMM are equal for low oxide voltages (lower than 0.5 V), while for higher oxide voltages only the tunneling currents computed under the Airy-wavefunction approach fit those obtained under the TMM. Therefore, the Airy-wavefunction approach provides a better analytical model to tunneling processes in the MOS capacitor.

Effects of high-k zirconium oxide (ZrO2) interlayer on the electrical and transport properties of Au/n-type InP Schottky diode

The structural, chemical, electrical and carrier transport properties of high-k ZrO2 on n-type InP with Au electrode have been studied by X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS), current-voltage (IV) and capacitance-voltage (CV) techniques at room temperature. Results show that the high barrier height is achieved for the Au/ZrO2/n-InP metal-insulator-semiconductor (MIS) diode as compared to the Au/n-InP metal-semiconductor (MS) diode. Using Cheung's functions, the barrier height, ideality factor and series resistance are estimated for the MS and MIS diodes. The barrier heights are determined by IV, Cheung's and surface potential-forward voltage plot for both the MS and MIS diodes which are found to be in good agreement with each other. Results indicate that the interface state density of Au/ZrO2/n-InP MIS diode is lower than that of Au/n-InP MS diode. This may be attributed to the fact that the introduction of the high-k ZrO2 interlayer led to reduction of the interface state density in the Au/n-InP MS diode. Results indicate that the Poole-Frenkel emission is the dominant conduction mechanism in the lower bias region while Schottky emission is dominant in the higher bias region for both the Au/n-InP MS and Au/ZrO2/n-InP MIS diodes.

Comparison between Si/SiO2 and InP/Al2O3 based MOSFETs

Electron transport properties of InP-based MOSFET as a new channel material with Al2O3 as a high-k dielectric oxide layer in comparison with Si-based MOSFET are studied by the ensemble Monte Carlo simulation method in which the conduction band valleys in InP are based on three valley models with consideration of quantum effects (effective potential approach). Id–Vd characteristics for Si-based MOSFET are in good agreement with theoretical and experimental results. Our results show that Id of InP-based MOSFET is about 2 times that of Si-based MOSFET. We simulated the diagrams of longitudinal and transverse electric fields, conduction band edge, average electron velocity, and average electron energy for Si-based MOSFET and compared the results with those for InP-based MOSFET. Our results, as was expected, show that the transverse electric field, the conduction band edge, the electron velocity, and the electron energy in a channel in the InP-based MOSFET are greater than those for Si-based MOSFET. But the longitudinal electric field behaves differently at different points of the channel.

Solution-processed high-k magnesium oxide dielectrics for low-voltage oxide thin-film transistors

Solution-processed metal-oxide thin films with high dielectric constants (k) have been extensively studied for low-cost and high-performance thin-film transistors (TFTs). In this report, MgO dielectric films were fabricated using the spin-coating method. The MgO dielectric films annealed at various temperatures (300, 400, 500, and 600 °C) were characterized by using thermogravimetric analysis, optical spectroscopy, X-ray diffraction, X-ray photoelectron spectroscopy, and atomic-force microscopy. The electrical measurements indicate that the insulating properties of MgO thin films are improved with an increase in annealing temperature. In order to clarify the potential application of MgO thin films as gate dielectrics in TFTs, solution-derived In2O3 channel layers were separately fabricated on various MgO dielectric layers. The optimized In2O3/MgO TFT exhibited an electron mobility of 5.48 cm2/V s, an on/off current ratio of 107, and a subthreshold swing of 0.33 V/dec at a low operation voltage of 6 V. This work represents a great step toward the development of portable and low-power consumption electronics.

Buffer layer engineering on graphene via various oxidation methods for atomic layer deposition

The integration of a high-k oxide on graphene using atomic layer deposition requires an electrically reliable buffer layer. In this study, Y was selected as the buffer layer due to its highest oxidation ability among the rare-earth elements, and various oxidation methods (atmospheric, and high-pressure O2 and ozone annealing) were applied to the Y metal buffer layer. By optimizing the oxidation conditions of the top-gate insulator, we successfully improved the capacitance of the top gate Y2O3 insulator and demonstrated a large Ion/Ioff ratio for bilayer graphene under an external electric field.

Low operating voltage organic transistors and circuits with anodic titanium oxide and phosphonic acid self-assembled monolayer dielectrics

We fabricated organic thin-film transistors (OTFTs) with sub-1 V driving voltage enabled by a hybrid dielectric comprising high-k amorphous titanium oxide (TiOx) and a phosphonic acid self-assembled monolayer (SAM). The p-type OTFTs show a high on/off ratio (105), a near 0 V threshold voltage (−0.09 V), and a high mobility of 1.2 cm2/Vs when operated at 1 V. These OTFTs are readily employed in circuit applications, and we show pseudo-CMOS and CMOS inverters operating at 0.5 V as basic building blocks of low-voltage advanced organic logic circuits. We fabricate a five-stage CMOS ring oscillator that displays clear oscillation characteristics at a driving voltage of 0.5 V to highlight the potential of our hybrid dielectric for ultra-low-voltage integrated plastic circuitry.

Energy band alignment of high-k oxide heterostructures at MoS2/Al2O3 and MoS2/ZrO2 interfaces

Substrate-induced electron energy band alignments of ultrathin molybdenum disulfide (MoS2) films are investigated using photoemission spectroscopy. Thin layer MoS2/Al2O3 and MoS2/ZrO2 interfaces show valence band offset (VBO) values of 3.21 eV and 2.77 eV, respectively. The corresponding conduction-band offset (CBO) values are 3.63 eV and 1.27 eV. Similarly, the calculated VBO and CBO values for an ultrathin layer of MoS2/SiO2 are estimated to be 4.25 and 2.91 eV, respectively. However, a very thick layer of MoS2 on Al2O3 and ZrO2 layers increases the CBO and VBO values by 0.31 eV and 0.2 eV, respectively, due to the shifting of the Mo 4dz2 band toward the Fermi level. The atomic force microscopy images show that the films are atomically smooth and favor the formation of a high-quality interface between the substrate and the film. The investigated luminescence spectra reveal that the MoS2 films show very strong interactions with different high-k surfaces, whereas the Raman spectrum is only weakly influenced by the different dielectric substrates. This interesting finding encourages the application of high-k oxide insulators as gate materials in MoS2-based complementary metal-oxide semiconductors and other electronic devices.

Solution Processing and Conversion of Transparent Metal Oxide Optical Coatings By Solid State Diffusion

Many modern technologies are based on materials that are deposited on special underlying materials. Optical coatings can prevent tarnishing, give anti-reflection benefits, and in some cases filter out harmful UV rays. In consumer devices, many modern optoelectronic devices that make up a vast majority of electronic products such as active displays, touch screens etc. are based thin film transistors and transparent materials, as are parts of solar cells, smart windows, antireflection coatings for a range of devices and applications, anti-fingerprint and antifogging glass, among many other modern uses of see-through materials and coatings with well-defined characteristics in visible light. While the science and technology of controlling materials into a whole host of electronics and photonic or optical devices has advanced considerably in the last decade, industry still requires all this to be done without using critical raw materials, expensive coating methods that are often very slow, and to do so at much lower temperatures for coating on to curved or flexible displays or materials – all without sacrificing quality that current methods provide. Here, we report a facile solution processed technique for the formation of a transparent thin film through an inter-diffusion process involving substrate dopant species at a range of low annealing temperatures compatible with processing conditions required by many state-of-the-art devices. The inter-diffusion process facilitates the movement of Si, Na and O species from the substrate into the as-deposited vanadium oxide thin film forming a composite fully transparent V0.0352O0.547Si0.4078Na0.01. Thin film X-ray diffraction and Raman scattering spectroscopy show the crystalline component of the structure to be α-NaVO3 within a glassy matrix. This optical coating exhibits high broadband transparency, exceeding 90-97% absolute transmission across the UV-to-NIR spectral range, while having low roughness and free of surface defects and pinholes. The production of transparent films for advanced optoelectronic devices, optical coatings, and low- or high-k oxides is important for planar or complex shaped optics or surfaces. It provides opportunities for doping metal oxides to new ternary, quaternary or other mixed metal oxides on glass, encapsulants or other substrates that facilitate diffusional movement of dopant species. References (1) C. Glynn, D. Creedon, H. Geaney, T. Collins, E. Armstrong, M. A. Morris and C. O'Dwyer, Sci. Rep., 5, 11574 (2015). (2) C. Glynn, D. Aureau, G. Collins, S. O'Hanlon, A. Etcheberry and C. O'Dwyer, Nanoscale, 7, 20227 (2015). (3) S. O'Hanlon, C. Glynn and C. O'Dwyer, ECS J. Solid State Sci. Technol., 5, R3100 (2016). (4) K. K. Banger, Y. Yamashita, K. Mori, R. L. Peterson, T. Leedham, J. Rickard and H. Sirringhaus, Nat. Mater., 2011, 10, 45-50. (5) K. Ellmer, Nat. Photon, 2012, 6, 809-817. (6) C. G. Granqvist, Thin Solid Films, 2014, 564, 1-38. (7) H. Dotan, O. Kfir, E. Sharlin, O. Blank, M. Gross, I. Dumchin, G. Ankonina and A. Rothschild, Nat. Mater., 2013, 12, 158-164. Figure 1

Influence of Channel Length and High-K Oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate Stack DG-MOSFETs

Comparative assessment of graded channel gate stack (GCGS) DG MOSFET structure is done by using two-dimensional (2D) Sentrausu TCAD simulator for different high K oxide thickness. This novel device includes gate stack (GS) engineering (high K) and nonuniformly channel engineering (GC) to suppress the short channel effects and improve the device performance. This novel device can be a better alternative for the future high speed switching and low power circuit applications. It has the advantage of improved breakdown voltage, reduced leakage current, low output conductance and reduced bipolar parasitic effects. The given device must be properly investigated with respect to the variation of different high K oxide thickness on different parameters such as drain induced barrier lowering (DIBL), subthreshold slope (SS), [Formula: see text]/[Formula: see text], [Formula: see text] roll off before fabrication to have better reliability. The 2D Sentrausu TCAD simulator using drift-diffusion model was used to simulate the developed structure and good agreement is obtained with respect to already published result in the sub-threshold regime. The result indicates that there is a need to be optimize the DC parameters for specific circuit applications.

The stability of aluminium oxide monolayer and its interface with two-dimensional materials.

The miniaturization of future electronic devices requires the knowledge of interfacial properties between two-dimensional channel materials and high-κ dielectrics in the limit of one atomic layer thickness. In this report, by combining particle-swarm optimization method with first-principles calculations, we present a detailed study of structural, electronic, mechanical, and dielectric properties of Al2O3 monolayer. We predict that planar Al2O3 monolayer is globally stable with a direct band gap of 5.99 eV and thermal stability up to 1100 K. The stability of this high-κ oxide monolayer can be enhanced by substrates such as graphene, for which the interfacial interaction is found to be weak. The band offsets between the Al2O3 monolayer and graphene are large enough for electronic applications. Our results not only predict a stable high-κ oxide monolayer, but also improve the understanding of interfacial properties between a high-κ dielectric monolayer and two-dimensional material.

Approaching Defect-free Amorphous Silicon Nitride by Plasma-assisted Atomic Beam Deposition for High Performance Gate Dielectric.

In the past few decades, gate insulators with a high dielectric constant (high-k dielectric) enabling a physically thick but dielectrically thin insulating layer, have been used to replace traditional SiOx insulator and to ensure continuous downscaling of Si-based transistor technology. However, due to the non-silicon derivative natures of the high-k metal oxides, transport properties in these dielectrics are still limited by various structural defects on the hetero-interfaces and inside the dielectrics. Here, we show that another insulating silicon compound, amorphous silicon nitride (a-Si3N4), is a promising candidate of effective electrical insulator for use as a high-k dielectric. We have examined a-Si3N4 deposited using the plasma-assisted atomic beam deposition (PA-ABD) technique in an ultra-high vacuum (UHV) environment and demonstrated the absence of defect-related luminescence; it was also found that the electronic structure across the a-Si3N4/Si heterojunction approaches the intrinsic limit, which exhibits large band gap energy and valence band offset. We demonstrate that charge transport properties in the metal/a-Si3N4/Si (MNS) structures approach defect-free limits with a large breakdown field and a low leakage current. Using PA-ABD, our results suggest a general strategy to markedly improve the performance of gate dielectric using a nearly defect-free insulator.

Hole mobility modulation of solution-processed nickel oxide thin-film transistor based on high-k dielectric

Solution-processed p-type oxide semiconductors have recently attracted increasing interests for the applications in low-cost optoelectronic devices and low-power consumption complementary metal-oxide-semiconductor circuits. In this work, p-type nickel oxide (NiOx) thin films were prepared using low-temperature solution process and integrated as the channel layer in thin-film transistors (TFTs). The electrical properties of NiOx TFTs, together with the characteristics of NiOx thin films, were systematically investigated as a function of annealing temperature. By introducing aqueous high-k aluminum oxide (Al2O3) gate dielectric, the electrical performance of NiOx TFT was improved significantly compared with those based on SiO2 dielectric. Particularly, the hole mobility was found to be 60 times enhancement, quantitatively from 0.07 to 4.4 cm2/V s, which is mainly beneficial from the high areal capacitance of the Al2O3 dielectric and high-quality NiOx/Al2O3 interface. This simple solution-based method for producing p-type oxide TFTs is promising for next-generation oxide-based electronic applications.