High-k Dielectric Materials Research Articles

Performance of High-k Dielectric Material for Short Channel Length MOSFET Simulated using Silvaco TCAD Tools

Performance of High-k Dielectric Material for Short Channel Length MOSFET Simulated using Silvaco TCAD Tools

A Feasible Alternative to FDSOI and FinFET: Optimization of W/La2O3/Si Planar PMOS with 14 nm Gate-Length.

At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (Ioff). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore’s Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using La2O3 as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters’ variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage (Vth) of −0.289 V ± 12.7% and Ioff of less than 10−7 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO2 formation at the Si interface and rapid annealing processing are required to achieve La2O3 thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on Vth, Ion and Ioff were investigated. The improved voltage scaling resulting from the lower Vth value is associated with the increased Ioff due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.

Enhanced infrared photoresponse of a new InGaZnO TFT based on Ge capping layer and high-k dielectric material

In this paper, a novel InGaZnO (IGZO) Infrared (IR) thin-film Phototransistor (Photo-TFT) consisting of Germanium capping layer (Ge-CL) and high-k dielectric material is proposed and numerically investigated. The role of introducing Ge-CL/IGZO heterojunction and high-k dielectric such as HfO 2 , ZrO 2 , Ta 2 O 5 and TiO 2 in achieving the dual benefit of IR photodetection ability and reduced dark noise effects is demonstrated. It is found that the proposed Ge-CL/IGZO Photo-TFT with appropriate gate oxide material can offer high detectivity of 2.3 × 10 14 Jones, superior current ratio exceeding 200 dB and high IR responsivity of 4.1 × 10 2 A/W. These enhancements are attributed to a mixture of two effects; firstly, the introduction of p-type Ge-CL leads to form a p-n junction with IGZO, thus enhancing the separation and transfer mechanisms of photo-induced electron/hole pairs. Secondly, the use of high-k dielectric materials enables better control of the channel conductivity , allowing reduced power consumption. Therefore, we believe that the use of Ge-CL with suitable high-k dielectric material pinpoints a new pathway to design high IR photoresponse sensors based on cost-effective IGZO TFT building block, which makes it potential alternative for high-performance optoelectronic systems. • A new high-performance IGZO-TFT-IR sensor is proposed. • The proposed sensor demonstrates high IR responsivity of 4.1 × 10 2 A/W. • A superb detectivity and an ultrahigh I ON /I OFF ratio are recorded. • The proposed sensor is a promising alternative for low power consumption photosensors.

Enhancement of Luminous Power and Efficiency in InGaN/GaN–Light Emitting Diode using high-k dielectric material

A novel high-k dielectric material is proposed for InGaN/GaN–LED to improve the performance. The proposed LED is analyzed and benchmarked with conventional LED using Technological Computer Aided Design (TCAD). The qualitative consistency of the optical characteristics of LED in this work has been observed that validate the TCAD simulation. Further, it is observed that proposed LED recorded higher luminous power and internal quantum efficiency (IQE) than that of conventional LED. At the injection current of 600 mA, the proposed and conventional LED yielded luminous power of 1600 mW and 1400 mW, respectively. Further, IQE of the proposed LED is higher than that of conventional LED by 12%. The improvement in the optical performance is attribute to high-k dielectric material induced additional electric field and radiative recombination rate. Thus, the proposed LED with high-k dielectric material is an outstanding device in lightning application.

Design, simulation and analysis of high-K gate dielectric FinField effect transistor

The devices with additional gates like Fin Field effect transistor (FinFET) provide higher control on subthreshold parameters and are favorable for Ultra large-scale integration. Also, these structures provide high control on current through the channel and with minimum leakage. In this paper we designed a FinFET with high-K gate dielectric material i.e Hafnium oxide as gate oxide. A comparison of similar sized transistor with Air and Silicon dioxide as gate material is performed. The comparison is mainly in terms of performance parameters like transconductance, subthreshold slope, and drain current characteristics. There is an increase in ON current on using a high-K dielectric material and subsequently an improvement in other parameters like subthreshold slope, transconductance and intrinsic gain.

Dielectric Pocket-Pocket Intrinsic Triple Gate TFET for Low Power Application: A Device Level Analysis

This report investigates a novel dielectric pocket—pocket intrinsic triple gate tunnel field effect transistor to magnify a device’s performance well suited for low-power applications. The source engineering which was adopted here using DP and PI has resulted in improved drive current of the device. A heterojunction was also formed between low bandgap energy materials and silicon, at the source side, to escalate the carrier tunneling at the interface of source and channel. Gate-drain overlapping technique, usage of high bandgap materials in drain region along with high-K dielectric materials in oxides ensured low ambipolar current, low off current, and a steeper subthreshold slope respectively. With these traits, the proposed device is believed to be suitable for low-power applications. The proposed structure is simulated, and the electrical parameters are analysed using the SILVACO TCAD ATLAS tool.

Improved photodetector performance of high-k dielectric material (La) doped V2O5 thin films as an interfacial layer in Schottky barrier diodes

In this work, high-k dielectric material of lanthanum (La) doped vanadium pentoxide (V2O5) thin films is deposited on glass substrate using spin coating route and annealed at 500 °C. The Cu/La-V2O5/n-Si Schottky barrier diodes with different La concentrations have fabricated. X-Ray Diffraction (XRD) characterization exposed the tetragonal crystal structure of La-V2O5 films. Field Emission Scanning Electron Microscopy (FE-SEM) morphology shows nanorod grain on La-V2O5 films. The decrease of optical gap (Eg) from 3.37 to 3.1 eV has been observed in UV-vis spectroscopy. The dc electrical conductivity is increased owing to the high-k-dielectric material influence of doping. Notably, La 4% doping exhibits high photo responsivity of 33.39 (mA/W) during fast switch response (ONOFF).

Redefining high-k dielectric materials vision at nanoscale for energy storage: A new electrochemically active protection barrier

Dielectric materials have been used for decades for energy applications where their insulation and polarizability properties are critical. In the energy storage field, most material scientists envision high-k dielectric layers in contact with an active material only as an insulating passivation layer. In microelectronics, this concept has been modified with the study of dielectrics at nanoscale level revealing interesting properties scarcely known by other fields. We propose to reconsider the vision of high-k dielectric materials for energy at nanoscale specifically. Based on microelectronic measurement techniques and nanometric control of dielectric thickness by Atomic Layer Deposition (ALD), an ultra-thin pinhole-free alumina (Al2O3) layer on a silicon nanowire (SiNW) is shown to display thickness dependent tunneling electrical conduction. This result brings a new light on this material class in the energy field and allows original approaches toward achieving scientific leaps. As an illustrative application, a silicon based micro-supercapacitor (MSC) protected by 3 nm of alumina dielectric layer exhibits Electrical Double Layer Capacitance (EDLC) by means of tunneling current in aqueous electrolyte, an unprecedented result for this material, with outstanding lifetime capacity retaining 99% of its initial capacitance after 2 million cycles. Extended to multiple energy materials, such method could lead to notable progress.

Comparative performance analysis based short channel effects for TG Nano FinFETs

The scaling down of CMOS technology has been carried out successfully following the Moore’s law for the last five decades. One of the main challenges for a nano scaled device are the Short Channel Effects (SCEs). It has begun to reach the limit of Silicon material; hence high-k dielectric materials are introduced to challenge the SCEs. Particularly HfO2 is used for this study. The high k dielectric material has been compared with the well-known SiO2 in a 3D SOI Tri-Gate (TG) FinFET device which is modelled and simulated in SILVACO TCAD tools. TG SOI FinFETs having 22nm,14nm and 10 nm channel lengths are developed. Since the device are in nano regime, short channel device parameters such as threshold voltage, subthreshold swing (SS), Ion current, Ioff current, Ion/Ioff ratio and DIBL are analysed for the two materials developed in TG SOI FinFET. The comparison shows that high k dielectric materials shows better results in reducing current leakage and drain induced barrier leakage than that of SiO2.

Effect of high-k dielectric material on the characteristics of Single Gate and Double Gate Multi-Channel Junctionless Nanowire Transistors

In this work, we have designed and analyzed the performance characteristics of n-type silicon based multi-channel junctionless nanowire transistors (JLNTs) for both single gate and double gate configurations. Numerical simulations using CVT (lambardi) model has been carried out to investigate the effects of different device parameters such as gate insulator dielectric, gate insulator thickness, and separating materials between channels. To illustrate and evaluate the performances, input characteristic curves, transconductance, and Ion/Ioff ratio of the devices have been extracted. It is observed that Ion/Ioff ratio are directly affected by the variation of dielectric and thickness of the gate. Devices having a high-κ dielectric provides steeper characteristics and better Ion/Ioff ratio for both the structures. The value of transconductance is also found to be greater for high-κ dielectric in both configurations with the double gate providing a higher value compared to the single one.

Low Power Circuit and System Design Hierarchy and Thermal Reliability of Tunnel Field Effect Transistor

Tunnel FET is one of the promising devices advocated as a replacement of conventional MOSFET to be used for low power applications. Temperature is an important factor affecting the performance of circuits or system, so temperature associated reliability issues of double gate Tunnel FET and its impact on essential circuit design components have been addressed here. The temperature reliability investigation is based on double gate Tunnel FET, containing Si1-xGe x /Si, source/channel and HfO2 high-k gate dielectric material. During investigation, it has been found that at high temperature application range ~ 300 K - to - 600 K,the Tunnel FET device design parameters exhibit weak temperature dependency with switching current (ION), while the off-state current (IOFF) is slightly varying ~10−17A/μm-to-10−10A/μm. In addition, the impact of temperature on various device design element such as VTH(i.e.,switching voltage),on-current (ION), off-current (IOFF), switching ratio (ION/IOFF) and average subthreshold slope (i.e., SSavg), ambipolar current (IAMB) have been done in this research work.The essential circuit design components for digital and analog/RF applications, such as current amplification factor(gm) and its derivative (gm’),the C-V components of device design, Cgg, Cgd and Cgs, cut - off frequency (ƒT) and gain band width (GBW) product have deeply investigated. In conclusion, the obtained results show that the designed double gate Tunnel FET device configuration and its circuit design components are suitable for ultra-low power circuit,system applications and reliable for hazardous temperature environment.

Hybrid electro-optic modulator combining silicon photonic slot waveguides with high-k radio-frequency slotlines

Electro-optic (EO) modulators rely on the interaction of optical and electrical signals with second-order nonlinear media. For the optical signal, this interaction can be strongly enhanced using dielectric slot–waveguide structures that exploit a field discontinuity at the interface between a high-index waveguide core and the low-index EO cladding. In contrast to this, the electrical signal is usually applied through conductive regions in the direct vicinity of the optical waveguide. To avoid excessive optical loss, the conductivity of these regions is maintained at a moderate level, thus leading to inherent RC limitations of the modulation bandwidth. In this paper, we show that these limitations can be overcome by extending the slot–waveguide concept to the modulating radio-frequency (RF) signal. Our device combines an RF slotline that relies on B a T i O 3 as a high-k dielectric material with a conventional silicon photonic slot waveguide and a highly efficient organic EO cladding material. In a proof-of-concept experiment, we demonstrate a 1 mm long Mach–Zehnder modulator that offers a 3 dB bandwidth of 76 GHz and a 6 dB bandwidth of 110 GHz along with a small π voltage of 1.3 V ( U π L = 1.3 V m m ). We further demonstrate the viability of the device in a data-transmission experiment using four-state pulse-amplitude modulation (PAM4) at line rates up to 200 Gbit/s. Our first-generation devices leave vast room for further improvement and may open an attractive route towards highly efficient silicon photonic modulators that combine sub-1 mm device lengths with sub-1 V drive voltages and modulation bandwidths of more than 100 GHz.

Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System

The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.

Analog/RF Performance of Graded Channel Gate Stack Triple Material Double Gate Strained-Si MOSFET with Fixed Charges

The performances of analog/RF parameters of a graded channel gate stack triple material double gate (GCGS-TMDG) strained-Silicon (s-Si) MOSFET with fixed charges are analyzed by using Sentaurus TCAD simulator. For the GCGS-TMDG s-Si MOSFET, analog/RF parameters, such as early voltage, transconductance generation factor (TGF), voltage gain, unity gain frequency (ft), gain frequency product (GFP), transconductance frequency product (TFP), and gain transconductance frequency product (GTFP), are estimated for various device parameters (i.e., strain in the silicon channel, fixed charge density with damaged length, and thicknesses of different high-k dielectric materials). The simulated data shows that the proposed GCGS-TMDG s-Si MOSFET obtains lower values of drain current and output conductance compared to the graded channel gate stack double gate (GCGS-DG) s-Si MOSFET. Besides, the GCGS-TMDG s-Si MOSFET provides superior performances of early voltage, ft, GFP, TFP, and GTFP in comparison with the GCGS-DG s-Si MOSFET in strong inversion region, and vice-versa in weak inversion region.

Analog/RF and Power Performance Analysis of an Underlap DG AlGaN/GaN Based High-K Dielectric MOS-HEMT

This paper exemplifies an exhaustive, figurative and subjective study on the RF performance and DC characteristics analysis of an Underlapped Double-Gate (U-DG) AlGaN/GaN heterojunction-based MOS-HEMT device with Hafnium-based high-k dielectric gate material. This paper depicts the effect of gate length variations on the drain current (ID), the transconductance (gm), the transconductance generation factor (gm/ID) and the RF FOMs intrinsic capacitances (CGD, CGS and CGG), intrinsic resistances (RGD and RGS), cut-off frequency (fT) and maximum oscillation frequency (fMAX). This study reveals shortening of channel length leading to better gate controllability hence an overall superior analog and RF performance is achieved. The U-DG AlGaN/GaN based MOS-HEMT device of 100 nm channel length shows a better Power Output Efficiency (POE) of 33% in contrast to 31% and 23% for the 200 nm and 300 nm devices respectively.

A surface potential model for tri-gate metal oxide semiconductor field effect transistor: Analysis below 10 nm channel length

In this study, an analytical model of Tri-gate metal-oxide-semiconductor field effect transistor (TGMOSFET) for short channel lengths below 10 nm is suggested and Technology computer-aided design (TCAD) simulation is used for confirmation. Two dimensional (2D) Poisson’s equation is solved with symmetric and asymmetric double gate (DG) MOSFET separately and is combined using the perimeter-weighted sum approach to model the surface potential of lightly doped silicon TGMOSFET. The model is examined by varying channel length, oxide thickness, gate voltage, drain voltage and doping concentration. In this study, the ratio of channel length to width is always kept greater than or equal to two. The structure is also inspected with a high-k dielectric material. A relative study of hafnium oxide (HfO2) and silicon dioxide (SiO2) with identical oxide thicknesses is given to explore the effect of high dielectric material on the model of TGMOSFET. To obtain identical surface potentials, the oxide thickness of HfO2 must be larger than SiO2. Unlike SiO2, the minima of surface potential remain constant with channel length for HfO2. The outcome of the TCAD simulation is highly associated with the results of the analytical model. Therefore, to meet high packing density and low power consumption, TGMOSFET can be a potential candidate for ultra large scale integrated circuit (ULSI) technology.

Capacitive Modeling of Cylindrical Surrounding Double-Gate MOSFETs for Hybrid RF Applications

The advancements in semiconductor technology greatly impact the growth of hybrid VLSI devices and components. The nanometer technology has been possibly executed due to the enhancement of the scaling factor of the MOSFETs. Since the MOSFETs play a vital role in building dense devices, it also has several research insights with various semiconductor materials with high-κ dielectrics. The high-κ dielectric material in place of the conventional oxide layer in the MOSFET design results in improved performance by reducing the Short Channel Effects (SCEs). In this research work, an analytical model of the lightly doped Cylindrical Surrounding Double-Gate (CSDG) MOSFET has been realized. The capacitive modeling has been done for this cylindrical structure. This modeling has been analyzed for all operating regions of the transistors, capacitance estimation, and electrical field dependence on the capacitance. The results have been compared with the previous research and tabulated. It has been observed that the transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) values have been raised to 0.0106 S/μm from 0.000645 S/μm with the inclusion of 2D electron gas in the core of CSDG MOSFET. This novel model occupies less area on the board, and routing is more accessible than the conventional DG MOSFET design. The overall results have been following the agreement in terms of accuracy, area tradeoff, and high speed, making the novel model suitable for high-frequency/RF applications.

Impact of High-k Dielectric Materials on Short Channel Effects in Tri-gate SOI FinFETs

Impact of High-k Dielectric Materials on Short Channel Effects in Tri-gate SOI FinFETs

Effect of High-k Dielectric Materials on Short Channel Effects of a 14 nm Tri-Gate SOI FinFET for Reduced Area on Chip

Effect of High-k Dielectric Materials on Short Channel Effects of a 14 nm Tri-Gate SOI FinFET for Reduced Area on Chip

Novel High-K SOI LDMOS with N+ Buried Layer

A novel high-K dielectric trench SOI LDMOS with an interface highly doped N buried layer (HKHN SOI LDMOS) is proposed. The devices are characterized with a high-K dielectric material (HK) introduced in the drift region and a high doping concentration of N existed below the HK trench (HKHN). First, the HK material causes assistant depletion in the N-drift region to increase doping concentration of the drift region (N d) and further improve the electric field (E-field) distribution. Second, the highly doped N buried layer below the interface of the HK trench can provide a low on-resistance passage and shorten the ionization integral path to enhance bulk field (ENBULF). Both the high drift region doping concentration and low on-resistance passage can reduce the specific on-resistance (R on,sp). Meanwhile, a higher breakdown voltage (BV) can be obtained by an optimized electric field distribution and a shortened ionization integration path. The new device can achieve high BV, low R on,sp and excellent figure of merit (FOM = BV 2/R on,sp). The BV of the HKHN SOI LDMOS is 552 V with R on,sp of 29.46 mΩ cm2 and FOM of 10.343 MW cm−2.