High Frequency Capacitance Voltage Research Articles

Influence of Outer Oxide Charges on the Electrostatics of Metal-Insulator-Semiconductor Tunnel Diode

Metal-Insulator-Semiconductor Tunnel Diode (MISTD) has an ultra-thin oxide with thickness less than 3.5 nm. When a MISTD is biased higher than a critical voltage V C, the device will be driven into the deep depletion region [1]. In this biasing condition, the electrostatics of the device will deviate from the behavior of traditional metal-oxide-semiconductor capacitors with thick oxide [1]. Thus, finding out the critical voltage V C is important to predict the electrostatics of a MISTD. In this work, we found that there is a systematic deviation of V C between the theoretical and the experimental values. A model considering the oxide-charge-induced lateral coupling (OCILC) is suggested as a possible mechanism leading to the deviation. With adding effective positive oxide charges of Q eff/q = 2.4-2.6×1011 cm-2, the calculated V C can fit well with the experimental observations.Figs. 1(a) and (b) are the band diagrams of MISTD biased at V TD < V C and V TD > V C, respectively, where V TD is the positive voltage applied on the metal. When V TD < V C, the generated electrons flow -J gen,bulk are able to follow the increase in the inversion charges and leakage current -J tunnel. In this situation, most of the applied V TD drops on the oxide, and the surface band bending of the silicon ψ s keeps around its initial value ψ 0, as shown in Fig. 1(a). In contrast, at V TD > V C, the generated electrons in original depletion region cannot follow the increase of the tunneling current. To keep the balancing of -J tunnel = -J gen,bulk, a large portion of V TD drops on the silicon and leads to an intense increase in ψ s, as shown in Fig. 1(b). The MISTD will operate under a significant non-equilibrium region under this bias condition. The balancing of -J tunnel = -J gen,bulk is finely discussed in [1].Ten MISTDs with distinct oxide thicknesses ranging from 23.7 to 34.4 Å were fabricated to extract V C. The device structure is shown in Fig. 2(a). The shape of the device is a circle with a diameter of 170 µm. From the measured high-frequency capacitance-voltage (HFCV) relations shown in Fig. 2(a), one can observe a flat region before a critical voltage and a quick decrease after the critical voltage. One can further extract surface band bending ψ s by HFCV [2]. The extracted q∆ψ/kT = q(ψ s-ψ 0)/kT is plotted in Fig. 2(b), where ∆ψ is the difference between ψ s and ψ 0. As the definition in [1], we extract V C at q∆ψ/kT = 3. The extract V C v.s. t ox is shown in Fig. 3 as solid symbols. At the same time, theoretical V C from the modeling proposed in [1] is also attached as a solid line. From Fig. 3, we observed a significant difference in V C between the modeling and the experimental.It is suggested that the OCILC causes the deviation of V C. The mechanism of OCILC is plotted in Fig. 4(a). The positive oxide charges outside the electrode will attract electrons at the silicon surface and form a lateral coupling channel. The potential applied on the electrode will laterally transport through the channel and collect the generated electrons from the lateral region. Finally, the balancing of electrons will become -J tunnel = -J gen,bulk-J gen,lateral, as shown in Fig. 4(b). Because of the extra supplement of electrons (-J gen,lateral), the MISTD can hold the quasi-equilibrium status to a higher voltage, and the V C increase. An improved model considering the effect of OCILC is proposed. The calculated result is plotted in Fig. 5. One can observe V C increase with Q eff. When positive Q eff/q is around 2.4-2.6×1011 cm-2, the calculated V C is close to the V C extract from the experimental.In conclusion, we suggested that the oxide charges outside the electrode play an important role in the electrostatics of MISTD. The mechanism of OCILC is proposed to explain the impact. A model considering OCILC is developed to calculate V C and the results fit well with the experimental results.This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 111-2221-E-192-MY3 and the National Science and Technology Council of Taiwan, ROC, under Contract No. NSTC 111-2622-8-002-001.[1] K. W. Lin, K. C. Chen and J. G. Hwu, An Analytical Model for the Electrostatics of Reverse-Biased Al/SiO₂/Si(p) MOS Capacitors With Tunneling Oxide, IEEE Trans. Electron Devices, 69, 1972, (2022)[2] E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology (Wiley, Hoboken) (1982) Figure 1

Influence of Outer Oxide Charges on the Electrostatics of Metal-Insulator-Semiconductor Tunnel Diode

In this work, the impact of outer oxide charges on the electrostatics of metal-insulator-semiconductor tunnel diodes (MISTD) is discussed. The existence of outer oxide charges will significantly affect the critical voltage V c of MISTD in the strong inversion region. At the bias voltage of V < V c, the MISTD works like a traditional metal-oxide-semiconductor (MOS) capacitor. However, at the bias voltage of V > V c, the MISTD goes to deep depletion. V c is an important boundary for the electrostatics behavior of MISTD. We propose a model, considering the existing outer oxide charges, to calculate V c and compare the calculated results with V c extracted from our devices. V c of our devices is extracted by measuring high-frequency capacitance-voltage (HFCV) at 300 kHz. It is found that the model is able to fit well with the experimental results when the amount of outer oxide charges is in the magnitude of 2.5×1011 cm-2 for our devices. The model is fundamental but helpful for analyzing and designing a MISTD.

The mechanism of heavy ion incident angle on the reliability of MOS device

Characterization for the influence of ion incident angle on single event effects (SEEs) in MOS device is essential to validate the current standard for space error rate. However, the response of angular effects induced by each incident ion is still an open question. Here, we pay attention to the differences of latent reliability degradation induced by different incident angles of swift heavy ions (SHIs). Specifically, HfO2 gate dielectric stacks were irradiated by 19.5 MeV/u 129Xe ions with the electronic energy loss ((dE/dx)e) of 29.9 keV/nm at different incident angles. The responses of electrical properties on heavy ion incidence angles were characterized by the high frequency capacitance-voltage (C-V) measurement after irradiation. We found that the dielectric properties of the HfO2 gate stacks degraded more and more dramatically as tilt angle increases, which results from the ion-induced latent tracks in amorphous HfO2. We propose that the microstructural damage induced by SHIs irradiation is one of the important factors influencing angular effects. This research is of great significance to estimate the vulnerability of electronic components used for space missions.

Extraction of Interface-Trap Densities of the Stacked Bonding Structure in 3D Integration Using High-Frequency Capacitance-Voltage Technique.

An extraction method of the interface-trap densities (Dit) of the stacked bonding structure in 3D integration using high-frequency capacitance–voltage technique is proposed. First, an accurate high-frequency capacitance–voltage model is derived. Next, by numerically solving the charge-balance equation and charge conservation equation, Dit is extracted by fitting the measured and calculated capacitance–voltage curves based on the derived model. Subsequently, the accuracy of the derived model is verified by the agreements between the analytical results and TCAD simulation results. The average extraction error proves the precision and efficiency of the extraction method. Finally, the stacked bonding structure has been fabricated, and Dit at the interface between silicon and insulator is extracted to diagnose and calibrate the fabrication processes.

Generation, relaxation and annealing of Si/SiO2 charges induced by low-energy electron beam

Silicon oxide based, aluminum gated MOS structures fabricated on n-type silicon were subjected to a low energy electron beam irradiation in the scanning electron microscope. The induced interface states and the oxide charges were studied by the high frequency capacitance–voltage technique as a function of the electron beam energy, irradiation dose, annealing time, temperature and electric field. Strong initial increase and subsequent saturation of the donor-like interface state density with the irradiation dose was observed for all electron beam energies used. Besides, shallow positively charged traps were found to be formed in the silicon oxide after irradiation, while at the initial stage of irradiation the formation of a negative charge was established. The irradiation induced interface states and the positively charged shallow oxide traps demonstrated notable reduction at room temperature. Zero bias annealing at the temperatures of about 250–300 °C resulted in a complete removal of the interface states and partial compensation or elimination of the oxidation induced positive fixed charge, presumably due to remaining negative charge in oxide.

Extraction of the Trench Sidewall Capacitances in an n-Type 4H-SiC Trench Metal– Oxide–Semiconductor Structure

In this work, a method was investigated to extract trench sidewall and trench bottom capacitances of a SiC trench metal-oxide-semiconductor (MOS) structure. Five groups of 4H-SiC trench MOS capacitors were designed and fabricated, with various trench bottom widths and trench mesa widths. High-frequency capacitance-voltage (HFCV) measurements at 100 kHz were performed on these trench MOS structures. The relationships between trench MOS capacitances and the widths of trench bottom as well as trench mesa were studied. As expected, under the same bias voltage, the measured trench MOS capacitances were proportional to the trench bottom widths and trench mesa widths. Based on this, the contributions of capacitances from the bottom, mesa, and sidewall of trench in trench MOS structure were studied systematically. The oxide thicknesses at different locations in trench were extracted. The C-V characteristics of the MOS capacitors from trench sidewall and trench bottom could also be deduced, from which the flat-band voltage and the charges in oxide of these two MOS capacitors could be subsequently calculated and analyzed. This method provides a convenient and precise technology to monitor process control in SiC trench MOSFETs manufacturing.

Changes in the structural and electrophysical properties of Ba0.8Sr0.2TiO3 films with decreasing thickness

Abstract Comparative studies of structural and electrophysical properties were performed for Ba0.8Sr0.2TiO3 (BSTO) films with the thickness of 100 nm, 120 nm and 350 nm. The surface morphology, the domain structure and local polarization switches were explored in the ferroelectric phase whereas high-frequency capacitance–voltage characteristics were measured in the paraelectric phase at 121°С. It was shown that good crystalline properties of the BSTO surface and grains are preserved until the thickness of ceramic layers decrease to 100 nm. The surface roughness did not exceed 2 – 4 nm and the average radius grains was in the range of 64 – 87 nm. Polarization domains induced with a microscope tip were stable and are conserved for several hours. Electrophysical properties of Ba0.8Sr0.2TiO3 films in the paraelectric phase strongly depend on the thickness of layers of BSTO ceramics. Effective dielectric permittivity of BSTO in the limit of weak fields decreases when the film thickness decreases from 350 nm to 100 nm from 920 to 400.

Effects of Very High Workfunction Metals or Metal Alloys (NiCr) on High Switching Speed, HV Schottky Diodes for Mixed Signal or RF ASIC

For high switching speed HV Schottky diodes, with very high work function metal and extremely lightly doped epi, the built-in potential may be too high for thermionic emission to occur, when the applied external voltage is quite low (near VF 0.07V). If the epi is lightly doped p type, the built-in potential (VBuilt-in: potential difference between the metal and silicon Fermi levels) is 1.0V (measured with CV). If the external bias is 0.1V, near the measured VF, it is not enough to overcome the built-in potential for thermionic emission as illustrated. It is likely that in addition to thermionic emission, tunnelling and diffusion currents also contribute to the total HV Schottky diode forward current. TCAD simulation of HV Schottky diodes with N+ guard bands suggests the potential barrier and electric fields at the Schottky junction are relatively high for thermionic emission to occur, when external bias V ≈ VF. In this paper we report HV Schottky diodes fabricated with various metals, metal alloys and epitaxial films. Metal work functions and epi doping profiles are extracted with high frequency Capacitance-Voltage (CV) technique. 150V of breakdown voltage and very low forward voltage (VF 0.07V) are demonstrated. The measured data indicate very high work function metal or metal alloy is needed to achieve high switching speed and low forward voltage.

Thermal and radiation response of 4H–SiC Schottky diodes with direct-write electrical contacts

A high-sensitivity 4H–SiC temperature sensor and an alpha detector have been fabricated using additively printed metal contacts. The surface morphology and electrical conductivity of the printed electrodes were established prior to Schottky diode development. 4H–SiC Schottky diodes with direct-write printed silver contacts on the 5 μm-thick epilayer on 4H–SiC were characterized electrically in terms of the forward and reverse current–voltage and high-frequency capacitance–voltage characteristics. The turn-on voltage of the Schottky diodes, as established from the forward current–voltage characteristics measured up to a temperature of 400 °C, showed a linear temperature dependence. Schottky diodes with direct-write printed Ag electrodes were able to measure alpha particles emitted from Americium-241. The high temperature and radiation response of the Schottky diodes show their suitability for multi-modal sensor fusion on the 4H–SiC platform for harsh environment applications.

Charging Effects in Al-SiO2-p-Si Structures After Low-Energy Electron Beam Irradiation

The effect of electron beam irradiation on trap charging and interface defect generation in Al/SiO2/Si structures was investigated by high-frequency capacitance–voltage measurements. Irradiation was carried out with two beam energies, at which the electron penetration depth was smaller and larger than the SiO2 thickness. The effect of applied bias, which changes the electric field inside the SiO2 film and the Si surface potential, on both the interface defect generation under the electron beam irradiation and their annealing was revealed. This showed that excess electrons generated by an e-beam play an important role in the interface defect formation. It was found that interface trap relaxation can occur even at room temperature, likely by electron tunneling from Si or hole tunneling from SiO2. The relaxation of positive bulk charge occurs at temperatures higher than 400 K via thermally stimulated carrier escape from traps. The activation energy for this process was estimated as 0.35–0.4 eV.

Capacitance voltage curve simulations for different passivation parameters of dielectric layers on silicon

Surface passivation is a widely used technique to reduce the recombination losses at the semiconductor surface. The passivating layer performance can be mainly characterized by two parameters: The fixed charge density (Qox) and the interface trap density (Dit) which can be extracted from Capacitance-Voltage measurements (CV). In this paper, simulations of High-Frequency Capacitance-Voltage (HF-CV) curves were developed using simulated passivation parameters in order to examine the reliability of measured results. The Dit was modelled by two different sets of functions: First, the sum of Gaussian functions representing different dangling bond types and exponential tails for strained bonds. Second, a simpler U-shape model represented by the sum of exponential tails and a constant value function was employed. These simulations were validated using experimental measurements of a reference sample based on silicon dioxide on crystalline silicon (SiO2/c-Si). Additionally, a fitting process of HF-CV curves was proposed using the simple U-shape Dit model. A relative error of less than 0.4% was found comparing the average values between the approximated and the experimentally extracted Dit’s. The constant function of the approximated Dit represents an average of the experimentally extracted Dit for values around the midgap energy where the recombination efficiency is highest.

Latent Reliability Degradation of Ultrathin Amorphous HfO2 Dielectric After Heavy Ion Irradiation: The Impact of Nano-Crystallization

The reliability degradation of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based devices under heavy ion irradiation is still an open question. In this letter, the ultrathin amorphous HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate stacks were irradiated by different types of swift heavy ions (SHIs). The fine structure of latent track in amorphous HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> is crystalline phase along the particle trajectory. The effects of latent track on the electrical properties were characterized by the high frequency capacitance-voltage (C-V) and the leakage current density-voltage (J-V) measurements. The quantitative relationship between microstructure changes and electrical properties provides a new method to estimate the threshold of the electronic energy loss ((dE/dx) <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</sub> ) for crystallization and allows for prediction of device sensitivity to SHIs irradiation.

A comprehensive technique for estimation of process-induced fixed charges and effective work function of the metal gate on high- stack

An efficient generalized methodology is proposed for precise estimation of process-induced various fixed charge distributions in the dielectric layer and extraction of the effective work function (EWF) of the metal gate on double layer high-κ/SiO2 stack in metal-oxide-semiconductor (MOS) capacitors. Present technique is equally applicable for devices grown on multiple wafers with varying as well as uniform doping concentrations. The analysis is verified with experimentally obtained high-frequency capacitance–voltage (C–V) results by varying only the physical thickness of the high-κ dielectric layer on an interfacial silicon dioxide (SiO2) film of a fixed thickness in MOS devices fabricated using a wide variety of high-κ metal gate (HKMG) technologies including the recent advanced 28 nm high performance logic technology node. Presence of significant amount of positive bulk charges in the high-κ layer, negative fixed charges at the high-κ/SiO2 interface in addition to fixed oxide charges and interface traps at the Si/SiO2 interface are observed from our analysis. Furthermore, we have observed a negligible amount of bulk positive charges compared to the effective positive charges at the Si/SiO2 interface in TaN/SiO2/ capacitors. The present analysis applied on bi-layer gate stacks with different high-κ materials viz hafnium oxide (HfO2) and aluminum oxide (Al2O3) and also on single layer SiO2 dielectric processed under various conditions, reveals that RTA in N2 results nitrogen related negative oxide charges at the Si/SiO2 interface. However, annealing in N2 has no significant effect on reduction of number of interface traps at the Si/SiO2 interface.

Improvement of the performance of ITO/a-SiOx/n-Si device by controllable sputtering power and reducible interface states

In order to methodically investigate the influence of sputtering power on interface states and performance of ITO/a-SiOx/n-Si device, the indium-tin oxide film (ITO) with thickness of 80 nm, was deposited on n-type silicon substrate by radio frequency magnetron sputtering. The device photovoltaic (PV) performance and the interface states of ITO/n-Si system were measured by solar simulator measurement system and the light-assisted high frequency capacitance-voltage (C–V) method, respectively. The experimental results demonstrate that the PV parameters of the ITO/a-SiOx/n-Si device achieve optimal values of PV parameters at 120 W (Voc~0.45 V, Jsc~28.57 mA/cm2, FF~71.20%, η~9.63%). Especially, the average interface state density (Dit) of ITO/n-Si interface drops from (1.29 ± 0.05) to (1.04 ± 0.02) × 1011 cm−2eV−1 when the sputtering power increases to 120 W, but the Dit sharply rises at higher sputtering power, which is negatively correlated with Voc and η. The effective minority carrier lifetime and O/Si ratio within interfacial layer were characterized by μ-PCD instrument and X-ray photoelectron spectroscopy, respectively. It is found that the device is well passivated by a-SiOx at 120 W. Moreover, the device performance is well-associated with the interface states and sputtering power.

Investigation of the Trap States and $V_{\text{TH}}$ Instability in LPCVD Si3N4/AlGaN/GaN MIS-HEMTs with an In-Situ Si3N4 Interfacial Layer

A novel gate and passivation dielectric stack consisting of a thin metal-organic chemical vapor deposition (MOCVD) grown in-situ Si3N4 (3 nm) and a thick low-pressure chemical vapor deposition (LPCVD) grown Si3N4 (30 nm) in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) is proposed. The quality of the Si3N4/(Al)GaN interface and the effect on threshold voltage ( ${V}_{\text {TH}}$ ) instability and dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ in the MIS-HEMTs with/without the in-situ Si3N4 layer are investigated by high-frequency capacitance-voltage (HFCV), quasi-static (QS) ${C}$ – ${V}$ (QSCV), time-of-fly (TOF) stress/measure, and QS ${I}_{\text {D}}$ – ${V}_{\text {DS}}$ methods. It is founded that the in-situ Si3N4 interfacial layer is effective in improving the dielectric/III-N interface morphology. As a result, better ${V}_{\text {TH}}$ stability and lower ${R} _{ \mathrm{\scriptscriptstyle ON},\text {D}}/{R} _{ \mathrm{\scriptscriptstyle ON},\text {S}}$ ratio are observed in devices with the in-situ Si3N4 interfacial layer due to the reduced density of traps close to the dielectric/III-N interface. Time-dependent dielectric breakdown and Weibull performance further verified that the proposed bilayer gate dielectric stack is a promising structure for the high-reliability power transistors.

Improvement of electrical properties of ZnS/CdTe-HgCdTe interface by (NH4)2S treatment

Effect of 20% aqueous ammonium sulphide treatment on electrical properties of ZnS/CdTe-HgCdTe interface was studied by using high frequency capacitance-voltage (C-V) measurements showing significant improvement in surface conditions. MIS structures were fabricated on passivated HgCdTe wafers and C-V measurements were carried out. C-V curves were analysed to evaluate fast interface state distribution with energy, slow state density and fixed charged density. For the sake of comparison two HgCdTe samples were prepared under similar conditions, one was given (NH4)2S treatment after standard surface preparation by I-KI polishing and the other was untreated to act as the base sample. CdTe and ZnS layers were deposited on both the samples, A and B. It was observed that C-V characteristics of (NH4)2S treated sample show significant improvement in comparison to that of untreated sample. Fixed charge density and fast interface charge (fast and slow) density were estimated for both the samples. Average fixed charge density for sample treated with (NH4)2S (4.2 × 1010 cm−2) is reduced by a factor of ~6 compared to untreated sample (2.53 × 1011 cm−2), Average fast interface trap density for sample exposed to (NH4)2S treatment (~3.5 × 1011 cm−2eV−1) improved by a factor of ~3.5compared to untreated sample (~1.3 × 1012 cm−2eV−1) while average slow interface traps estimated for sample treated with (NH4)2S (~3.09 × 1010 cm−2) reduced by ~1.3times than that for untreated sample (~4.1 × 1010 cm−2). Surface and interface stability of the grown sulphide is also studied by repeated ellipsometry and C-V measurements respectively. It is found that it is important to deposit CdTe/ZnS passivation layers immediately after 20% aqueous ammonium sulphide treatment to achieve stable performance. Stability of (NH4)2S treatment with time was also investigated. C-V measurements after approximately 2 months showed improvement in interface properties.

Characterization of Deep and Shallow Traps in GaN HEMT Using Multi-Frequency C-V Measurement and Pulse-Mode Voltage Stress

In this paper, the influence of interface traps at the SiN/GaN interface and carbon-related buffer traps on GaN high electron mobility transistor (HEMT) on silicon substrate has been studied using high-frequency capacitance-voltage (HFCV) and quasi-static C-V (QSCV) measurement. The correlation between dynamic resistance degradation and trap density distribution subjected to pulse stress conditions has been examined. Deeper-level traps from the hole-emission process of the carbon-related buffer layer are activated by high drain voltage during off-state stress, and shallow-level traps at the SiN interface are enhanced by an increase in gate voltage during the on-state stress. 2-D device simulations have been carried out to probe the physical insight into the dynamic resistance degradation. Good agreement between experimental data and simulated results is obtained while taking into account shallow-level and deeper-level traps.

Evaluation of interface trap characterization methods in 4H-SiC metal oxide semiconductor structures over a wide temperature range

In this paper, four widely used interface trap characterization methods based on quasistatic and high-frequency capacitance–voltage (CV) and conductance–frequency (Gω) measurements are evaluated at thermally oxidized 4H-SiC metal oxide semiconductor structures. To cover a wide range of defect levels in a wide bandgap semiconductor, the CV and Gω measurements are conducted at temperatures ranging from 150 to 600 K. Interface trap densities Dit are extracted using the high-frequency Terman method, the low frequency capacitance method, the high-low frequency method, and the conductance method. A very good agreement between the different methods is observed in restricted energy ranges. The use of the conductance method allowed for the determination of defect states in an energy range of almost 800 meV. A strong hysteresis of bidirectional CV curves is observed at different temperatures and is used to estimate border trap densities. The presence of mobile charges in the oxide is found to be a limiting factor for high temperature CV measurements. Low temperature Gω measurements revealed a second conductance peak which is identified as the 100 meV nitrogen donor level.

Post deposition annealing effect on properties of Y2O3/Al2O3 stacking gate dielectric on 4H-SiC

In this paper, the effect of post deposition annealing (PDA) on the chemical, structural, and electrical properties of the high-k Y2O3/Al2O3 stacking dielectric on p-type 4H-SiC were studied. High-k dielectric provides a physically thicker film with equivalent capacitance, therefore better exploits the high breakdown strength of 4H-SiC in its MOSFET devices. The Y2O3/Al2O3 stacking films were deposited using RF magnetron sputtering, with PDA in Ar ambient at 400 °C, 600 °C, 800 °C and 1000 °C. X-ray diffraction (XRD) and angle resolved X-ray photoelectron spectroscopy (XPS) results show that an Al5O12Y3 crystal layer was formed in between Y2O3 and Al2O3 films after annealing above 600 °C. High resolution transmission electron microscope (HRTEM) was used to investigate the atomic structure and measure the thickness of each layer. Charges and dielectric strength of the stacking films were characterized by high frequency capacitance-voltage (C-V) and current-voltage (I-V) measurements. The lower charge density and higher dielectric strength were found after PDA at 800 °C and 1000 °C.

Investigation of resistive switching in SiO2 layers with Si nanocrystals

MOS structures with two-layer insulator, SiO2/SiOx, are tested for switching between high and low resistance state. Part of the structures were annealed at 1000 °C for 60 min in N2 in order to form silicon nanocrystals (Si NCs) in a SiOx matrix. Cross-sectional transmission electron microscopy revealed that after the high temperature annealing phase separation takes place and nanocrystals with size of ∼ 4–5 nm are formed. Direct current–voltage measurements showed that bipolar switching occurs only in the annealed c–Si/SiO2/SiOx/Al structures and not in the control samples. A model explaining the resistance change by electric field formation of conductive pathway in the SiOx-Si NCs layer at negative gate voltages and current driven destruction of the conductive filament at positive voltages was verified by high frequency capacitance-voltage (C-V) measurements. From the C-V results the dielectric constant of non-annealed SiOx films with x = 1.3 was calculated to be εSiOx = 4.6.