A comprehensive technique for estimation of process-induced fixed charges and effective work function of the metal gate on high- stack

Abstract

An efficient generalized methodology is proposed for precise estimation of process-induced various fixed charge distributions in the dielectric layer and extraction of the effective work function (EWF) of the metal gate on double layer high-κ/SiO2 stack in metal-oxide-semiconductor (MOS) capacitors. Present technique is equally applicable for devices grown on multiple wafers with varying as well as uniform doping concentrations. The analysis is verified with experimentally obtained high-frequency capacitance–voltage (C–V) results by varying only the physical thickness of the high-κ dielectric layer on an interfacial silicon dioxide (SiO2) film of a fixed thickness in MOS devices fabricated using a wide variety of high-κ metal gate (HKMG) technologies including the recent advanced 28 nm high performance logic technology node. Presence of significant amount of positive bulk charges in the high-κ layer, negative fixed charges at the high-κ/SiO2 interface in addition to fixed oxide charges and interface traps at the Si/SiO2 interface are observed from our analysis. Furthermore, we have observed a negligible amount of bulk positive charges compared to the effective positive charges at the Si/SiO2 interface in TaN/SiO2/ capacitors. The present analysis applied on bi-layer gate stacks with different high-κ materials viz hafnium oxide (HfO2) and aluminum oxide (Al2O3) and also on single layer SiO2 dielectric processed under various conditions, reveals that RTA in N2 results nitrogen related negative oxide charges at the Si/SiO2 interface. However, annealing in N2 has no significant effect on reduction of number of interface traps at the Si/SiO2 interface.