Efficient methodology for estimation of metal effective work function, interface trap, and fixed oxide charges in metal-oxide-semiconductor capacitors with dual layer high-κ/SiO2 dielectric

Abstract

A capacitance-voltage (C–V) based efficient methodology is demonstrated for precise estimation of process-induced various fixed charge distributions in the dielectric layer, interface trapped charges at the silicon/oxide interface, and the effective work function (EWF) of the metal gate on double layer high-κ/silicon dioxide (SiO2) stack in metal-oxide-semiconductor (MOS) capacitors. The present technique takes care of the variation of the work function of the silicon substrate either due to wafer-to-wafer variation or nonuniformity of the doping level throughout the entire wafer. The analysis is verified with experimentally obtained high-frequency C–V results by varying only the physical thickness tHfO2 of the hafnium oxide (HfO2) dielectric layer on an interfacial SiO2 film of a fixed thickness tox in tantalum nitride (TaN)/HfO2/SiO2/p-Si MOS diodes. A value of 4.5 eV was obtained for EWF of physical vapor deposited TaN on HfO2. Furthermore, the calculations indicate the presence of a significant amount of positive bulk charges in the high-κ layer, in addition to interface trapped positive charges Qit at the Si/SiO2 interface and negative effective charges at both the high-κ/SiO2 and Si/SiO2 interfaces.