Abstract
An extraction method of the interface-trap densities (Dit) of the stacked bonding structure in 3D integration using high-frequency capacitance–voltage technique is proposed. First, an accurate high-frequency capacitance–voltage model is derived. Next, by numerically solving the charge-balance equation and charge conservation equation, Dit is extracted by fitting the measured and calculated capacitance–voltage curves based on the derived model. Subsequently, the accuracy of the derived model is verified by the agreements between the analytical results and TCAD simulation results. The average extraction error proves the precision and efficiency of the extraction method. Finally, the stacked bonding structure has been fabricated, and Dit at the interface between silicon and insulator is extracted to diagnose and calibrate the fabrication processes.
Highlights
Three-dimensional (3D) integration has emerged as one possible approach to overcome the challenges of “More Moore” applications with the advantages of high-density integration, small form factor, high performance, low power consumption and multiple functionality of integrated circuits (ICs) [1,2]
Integration prior to ICs’ fabrication and monitoring unit of fabricating 3D ICs. It is divided into five layers: the silicon layer, the insulator layer, the metal layer, the insulator layer and the silicon layer
In order to verify the precision and accuracy of the high-frequency capacitance–voltage model and Dit extraction, the staked bonding structure is investigated through Sentaurus
Summary
Three-dimensional (3D) integration has emerged as one possible approach to overcome the challenges of “More Moore” applications with the advantages of high-density integration, small form factor, high performance, low power consumption and multiple functionality of integrated circuits (ICs) [1,2] It sequentially stacks multi-layer integrated circuit chips and realizes electrical signal connection between multiple layers through monolithic inter-tier vias [3]. It is important to extract Dit of the 3D stacked bonding structure to improve performance, diagnosis and calibrate designs. Of the 3D stacked bonding structure to improve performance, diagnosis and calibrate deandand fabrication processes, including bonding, annealing, oxidation, etc.etc. The investigated structure presents complicated high-frequency capacvoltage characteristics with interface traps,traps, the method is accurate and independent of the itance–voltage characteristics with interface the method is accurate and independhigh-frequency capacitance–voltage curves. The investigated structure presents complicated high-frequency capacvoltage characteristics with interface traps,traps, the method is accurate and independent of the itance–voltage characteristics with interface the method is accurate and independhigh-frequency capacitance–voltage curves. curves
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