High-density Nonvolatile Memory Research Articles

Effects of overlayer capping and lattice strain on perpendicular magnetic anisotropy of TM|FePt|MgO heterostructures

Magnetic tunnel junctions (MTJs) with ferromagnetic electrodes possessing the strong perpendicular magnetocrystalline anisotropy (PMA) are of great interest as they have a potential for realizing next-generation high-density non-volatile memory and logic chips. To date, it is an urgent and critical issue to continuously promote the PMAs through feasible modifications such as the substitution of ferromagnetic layers as well as the overlayer coating on them. Here, we perform the relativistic first principles calculations of TM|L10-FePt|MgO sandwich systems, and demonstrate that the changes in PMAs by capping TM layers are always giant and positive, e.g., PMA of Fe|FePt|MgO, the largest one among all our studied systems, is about 2 times larger than that of FePt|MgO. The interfacial PMAs at TM|FePt and FePt|MgO interfaces are extracted to be 3.31~9.40 meV and 3.32 meV, respectively, which are at least 3 times larger than 0.93 meV/ML of interior FePt layer. We illustratively verify that PMAs of TM|FePt|MgO can be turned in a large range by varying the TM layer and in-plane strain. Our results and model analyses provide useful insights for how these magnetic quantities are linked, and pave a way for the promotion of PMAs of FePt-based heterostructures via contact with TM overlayers.

Integration of graphene oxide buffer layer/graphene floating gate for wide memory window in Pt/Ti/Al2O3/GO/graphene/SiO2/p-Si/Au non-volatile (FLASH) applications

The excellent electronic properties of graphene such as high density of states, work-function, and low dimensionality promote the usage of graphene as an efficient floating gate (FG) layer for downscaled, high density non-volatile flash memories (NVFMs). However, the chemical inertness of graphene requires a buffer layer for the uniform deposition of a high-k blocking layer (high-k blocking oxide/buffer layer/graphene/SiO2/p-Si/Au). Herein, FG-NVFM devices are fabricated using few-layer graphene as a FG followed by deposition of spin-coated monolayer graphene oxide (GO) as a buffer layer. The simple, stress free deposition of GO decorated with the functional groups is anticipated for the uniform deposition of blocking oxide (Aluminum oxide, Al2O3) over GO/graphene/SiO2/p-Si/Au. Beyond this, it improves the interface (Al2O3/GO/graphene), leading to enhanced memory characteristics for the fabricated Pt/Ti/Al2O3/GO/graphene/SiO2/p-Si/Au FG-NVFM structure. The electrical characterizations of the fabricated FG-NVFM devices show a significantly wide memory window of ∼4.3 V @ ±7 V at 1 MHz and robust retention up to ∼2 × 1013 s (>15 years). These observations clearly reveal an efficient potential of graphene for FG and GO as a buffer layer for the future NVFM device applications.

Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm × 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

High-Density NAND-Like Spin Transfer Torque Memory With Spin Orbit Torque Erase Operation

We present a NAND-like spintronics memory (NAND-SPIN) device for high-density non-volatile memory applications. Fast erasing and programming of magnetic tunnel junction (MTJ) are implemented with two unidirectional currents generating spin orbit torque (SOT) and spin transfer torque (STT), respectively. The asymmetric switching drawback of STT mechanism can be definitively overcome as only anti-parallel to parallel operation happens for NAND-SPIN programming, which allows lower switching current, smaller access transistor, and reduced maximum write voltage across the MTJ. By sharing the SOT-induced erase operation in a nanowire, the area overhead due to the three-terminal structure can be also eliminated. Simulation results show that NAND-SPIN can achieve 3 ~ 5× reduction in write energy compared to STT-MRAM, and 2 ~ 4× less bit-cell area than SOT-MRAM at 28 nm node.

Micromagnetic Calculation for Magnetic Tunnel Junctions With Equal Parallel and Antiparallel Thermal Stability

In magnetic tunnel junctions (MTJs) with perpendicular magnetic easy axes, the retention times for parallel and antiparallel states are different because of dipolar coupling with the reference layer (RL). To make retention times symmetrical, we model three types of MTJs that have single or synthetic ferrimagnetic (SyF) RLs with stepped structures. Micromagnetic calculations are performed on the basis of the Landau–Lifshitz–Gilbert equation of motion to evaluate the stray fields from the RLs of each design. A SyF structure with a step on the bottom magnetic layer has the smallest stray field of 2 mT at lateral dimensions of 30 nm × 30 nm in the layer. Symmetric thermal stability for parallel and antiparallel states should help to realize high-density nonvolatile magnetic random-access memory and logic chips.

Characteristics of multilevel storage and switching dynamics in resistive switching cell of Al2O3/HfO2/Al2O3 sandwich structure

We reported an Al2O3/HfO2/Al2O3 sandwich structure resistive switching device with significant improvement of multilevel cell (MLC) operation capability, which exhibited that four stable and distinct resistance states (one low resistance state and three high resistance states) can be achieved by controlling the Reset stop voltages (VReset-stop) during the Reset operation. The improved MLC operation capability can be attributed to the RHRS/RLRS ratio enhancement resulting from increasing of the series resistance and decreasing of leakage current by inserting two Al2O3 layers. For the high-speed switching applications, we studied the initial switching dynamics by using the measurements of the pulse width and amplitude dependence of Set and Reset switching characteristics. The results showed that under the same pulse amplitude conditions, the initial Set progress is faster than the initial Reset progress, which can be explained by thermal-assisted electric field induced rupture model in the oxygen vacancies conductive filament. Thus, proper combination of varying pulse amplitude and width can help us to optimize the device operation parameters. Moreover, the device demonstrated ultrafast program/erase speed (10 ns) and good pulse switching endurance (105 cycles) characteristics, which are suitable for high-density and fast-speed nonvolatile memory applications.

Kinetics of Domain Switching by Mechanical and Electrical Stimulation in Relaxor-Based Ferroelectrics

With their domain switching under electrical loading or mechanical stress, ferroelectric materials have been studied for applications in high-density nonvolatile memory. However, backswitching in such systems could cause significant data loss. In this work, experiments and stimulations are used to investigate the unique ferroelastic domain-switching kinetics of single-crystalline pillars of relaxor material. The electromechanical hysteresis loop shifts due to constraint of the pillars, resulting in various mechanically reversible $o\phantom{\rule{0}{0ex}}r$ $i\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}v\phantom{\rule{0}{0ex}}e\phantom{\rule{0}{0ex}}r\phantom{\rule{0}{0ex}}s\phantom{\rule{0}{0ex}}i\phantom{\rule{0}{0ex}}b\phantom{\rule{0}{0ex}}l\phantom{\rule{0}{0ex}}e$ states. This behavior could be exploited to overcome the backswitching problem in advanced bit writing and reading.

Fabrication of epitaxial ferroelectric BiFeO3 nanoring structures by a two-step nano-patterning method

A novel two-step nano-patterning method is proposed to fabricate epitaxial ferroelectric BiFeO3 (BFO) nanoring array, which maintains well-epitaxial structure and possesses strong ferroelectricity demonstrated by X-ray diffraction (XRD) and piezoresponse force microscopy (PFM). The ferroelectric polarizations were examined by PFM, revealing the reversible switching behavior under an electric field. This novel method could also be extended to other oxide material systems. The fabrication of high quality ferroelectric nanoring structure provides the possibility to explore novel functionalities (e.g., ferroelectric vortices) and offers application potentials for the high-density non-volatile memory devices.

(Invited) Relationship between Ferroelectricity and Electrical Breakdown in Hf-Zr-O Thin Films

Ferroelectricity of HfO2-based thin films is a new physical property discovered in 2011. This property is now expected to utilize in the development of high-density non-volatile memories and ferroelectric-gate FETs on LSI. In order to apply the ferroelectricity in electron devices, it is important to examine the correlation between the ferroelectricity and other electrical properties. In this work, we deposited Hf-Zr-O films by sputtering, fabricated metal/ferroelectric/metal capacitors, and examined their electrical properties. Relationship between the ferroelectric properties of remnant polarization and coercive field and the dielectric properties of dielectric constant and breakdown field were investigated by changing the thickness and metal composition of Hf-Zr-O films. Through the analyses, the determinant factor of electrical breakdown in HfO2-based ferroelectric films is discussed.

Investigation of multilevel data storage in silicon-based polycrystalline ferroelectric tunnel junction

Multilevel data ferroelectric tunnel junction is a breakthrough for further improving the storage density of ferroelectric random access memories. However, the application of these ferroelectric tunnel junctions is limited by high cost of epitaxial perovskite heterostructures, unsatisfactory retention and difficulty of exactly controlling the middle polarization states. In order to overcome the issues, we develop a ferroelectric tunnel junction with smooth ultrathin polycrystalline BiFeO3 (BFO) film. Through controlling the polarization state and oxygen vacancy migration using voltage pulses, we demonstrate that voltage-controlled barrier yields a memristive behavior in the device, in which the resistance variations exceed over two orders of magnitude. And we achieve multi logic states written and read easily using voltage pulses in the device. Especially the device is integrated with the silicon technology in modern microelectronics. Our results suggest new opportunity for ferroelectrics as high storage density nonvolatile memories.

Ultra-large non-volatile modulation of magnetic moments in PbZr0.2Ti0.8O3/MgO/La0.7Sr0.3MnO3 heterostructure at room temperature via interfacial polarization mediation

Multiferroic hybrid structures PbZr0.2Ti0.8O3 (PZT)/La0.7Sr0.3MnO3 (LSMO) and PZT/MgO/LSMO were epitaxially deposited on (001) Nb:SrTiO3 crystals. Crystallinity and ferroelectric domain structures were investigated for the PZT/LSMO heterostructure. Interestingly, relatively high non-volatile magnetoelectric coupling effects were observed in both heterostructures at room temperature. The change of chemical valence for Mn and Ti at the PZT/MgO/LSMO interface may play a dominant role rather than external strain or orbital reconstruction, which lead to a large modulation of the magnetization. Correspondingly, the transport behavior of the PZT/MgO/LSMO heterostructure is investigated to confirm the role of oxygen vacancies motion. Our result indicates that the PZT/MgO/LSMO heterostructure have a promising application for future high-density non-volatile memories.

New photopatternable polyimide and programmable nonvolatile memory performances

We report the first photopatternable, nonvolatile memory consisting of high-temperature polyimide (PI), poly(hexafluoroisopropylidenediphthalimide-4-cinnamoyloxytri-phenylamine) (6F-HTPA-CI), and we demonstrate the successful fabrication and programmable operation of ‘write-read-erase’ memory devices based on nanoscale thin films of 6F-HTPA-CI. The PI thin film enables scalable fine patternability, providing lines and spaces with excellent pattern fidelity. Isolated individual memory devices were successfully fabricated on a bottom electrode via a sequential process of coating, photopatterning, top electrode deposition, developing, rinsing and drying. The 6F-HTPA-CI cells exhibited excellent nonvolatile memory performances in three different modes (unipolar permanent, unipolar flash and bipolar flash memories), regardless of photo-exposure doses. The switching-ON (writing) voltage was in the range of ±1.5 to ±2.0 V, and the switching-OFF (erasing) voltage was in the range of ±0.3 to ±0.8 V; these voltages are quite low, indicating that power consumption by the devices during operation is low. The ON/OFF current ratio of the devices was in the range of 104–109. Overall, the photopatternable PI 6F-HTPA-CI opens up the possibility of low-cost mass production of high-performance, high-speed, energy-efficient, permanent or rewritable high-density nonvolatile polymer memory devices suitable for future advanced electronics in highly integrated systems.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

A high-density nonvolatile associative memory (NV-AM) based on spin transfer torque magnetoresistive random access memory (STT-MRAM), which achieves highly concurrent and ultralow-power nearest neighbor search with full adaptivity of the template data format, has been proposed and fabricated using the 90 nm CMOS/70 nm perpendicular-magnetic-tunnel-junction hybrid process. A truly compact current-mode circuitry is developed to realize flexibly controllable and high-parallel similarity evaluation, which makes the NV-AM adaptable to any dimensionality and component-bit of template data. A compact dual-stage time-domain minimum searching circuit is also developed, which can freely extend the system for more template data by connecting multiple NM-AM cores without additional circuits for integrated processing. Both the embedded STT-MRAM module and the computing circuit modules in this NV-AM chip are synchronously power-gated to completely eliminate standby power and maximally reduce operation power by only activating the currently accessed circuit blocks. The operations of a prototype chip at 40 MHz are demonstrated by measurement. The average operation power is only 130 µW, and the circuit density is less than 11 µm2/bit. Compared with the latest conventional works in both volatile and nonvolatile approaches, more than 31.3% circuit area reductions and 99.2% power improvements are achieved, respectively. Further power performance analyses are discussed, which verify the special superiority of the proposed NV-AM in low-power and large-memory-based VLSIs.

Gate contact resistive random access memory in nano scaled FinFET logic technologies

A full logic-compatible embedded gate contact resistive random access memory (GC-RRAM) cell in the CMOS FinFET logic process without extra mask or processing steps has been successfully demonstrated for high-density and low-cost logic nonvolatile memory (NVM) applications. This novel GC-RRAM cell is composed of a transition metal oxide from the gate contact plug and interlayer dielectric (ILD) in the middle, and a gate contact and an n-type epitaxial drain terminal as the top and bottom electrodes, respectively. It features low-voltage operation and reset current, compact cell size, and a stable read window. As a promising embedded NVM solution, the compact one transistor and one resistor (1T1R) cell is highly scalable as the technology node progresses. Excellent data retention and cycling capability have also been demonstrated by the reliability testing results. These superior characteristics make GC-RRAM one of a few viable candidates for logic NVM for future FinFET circuits.

Variability-Aware Analysis of Hybrid MTJ/CMOS Circuits by a Micromagnetic-Based Simulation Framework

Magnetic tunnel junctions (MTJs) are attracting an increasing interest due to their potentiality for high-density nonvolatile memories. However, some issues need to be opportunely considered in the design and optimization of hybrid MTJ/CMOS circuits, such as the stochastic nature of the MTJ switching, the high write energy consumption and the susceptibility to process variations. In this paper, we evaluate the impact of both MTJ and CMOS variability on the performance of basic hybrid MTJ/CMOS circuits in state-of-the-art nanoscale technologies. To this purpose, we exploit a simulation framework combining micromagnetic and electrical simulations. Full micromagnetic simulations are used to predict the MTJ behavior in terms of magnetoresistance-current hysteresis loop and statistical distribution of the switching delay as a function of the applied current. Those data are used to set up a look-up-table-based MTJ Verilog-A model to be used in commercial electrical simulators. Considering an MTJ with a diameter of 30 nm and a 28-nm fully-depleted silicon-on-insulator CMOS technology, we have exploited the above simulation framework to perform a variability-aware analysis on the write operation of a 1-MTJ writing circuit for nonvolatile flip-flops and a 256 × 256 STT-MRAM array. Our results show that the voltage scaling can be a promising approach for energy minimization in hybrid MTJ/CMOS circuits at the expense of larger area.

Large enhanced perpendicular magnetic anisotropy and thermal stability in Ta/CoFeB/MgO films with excess boron

The discovery of perpendicular magnetic anisotropy(PMA) in Ta/CoFeB/MgO film and the demonstration of high performance perpendicular magnetic tunnel junction(p-MTJ) based on this material system have accelerated the development of the next-generation high-density non-volatile memories and other spintronic devices. Currently it is urgently needed to improve the interfacial PMA and thermal stability of the CoFeB/MgO system for practical applications. So far, the perpendicularly magnetized CoFeB/MgO films and the corresponding p-MTJs have been extensively explored with the B content of the CoFeB layer mostly fixed at about 20 atomic percent. In this paper, four sets of multilayered films Ta/(Co0.5Fe0.5)1-xBx/MgO(x=0.1, 0.2, 0.3) and MgO/(Co0.5Fe0.5)0.7B0.3/Ta with different CoFeB thickness are deposited on thermally oxidized Si substrates by magnetron sputtering at room temperature, and subsequently they are annealed in high vacuum at different temperatures ranging from 573 to 623 K. The room temperature magnetic properties of the annealed samples are characterized by using vibrating sample magnetometer and superconducting quantum interference device magnetometer. With normal B content of 20% for the CoFeB layer, the Ta/CoFeB/MgO structure annealed at 573 K shows perpendicular magnetization when the CoFeB layer is no thicker than 1.2 nm. As the B content decreases to 10%, it has been found that PMA is achieved only in the sample with a 0.8 nm CoFeB layer under the same annealing condition. The result shows that the interfacial PMA appreciably falls off when the B content is reduced by half. On the other hand, when the B content of the CoFeB layers increases from 20% to 30%, the Ta/CoFeB/MgO structure annealed at 573 K exhibits PMA with the CoFeB layer as thick as 1.4 nm and the interfacial PMA(Ks) increases from 1.710-3 Jm-2 to 1.910-3 Jm-2 together with slightly improved thermal stability. Most remarkably, the MgO/CoFeB/Ta structure with 30% B shows optimum annealing temperature of about 623 K, at which Ks reaches 2.010-3Jm-2 and PMA is realized in the samples with the CoFeB thickness up to 1.5 nm. In contrast, the same structure with 20% B is magnetically destroyed completely under this annealing temperature. The present results suggest that the CoFeB layer with excess B can effectively improve the perpendicular magnetic properties and thermal stability for the Ta/CoFeB/MgO system, and one should take into account the B content effect to optimize the spintronic devices based on the perpendicularly magnetized CoFeB/MgO system.

Effects of bottom electrode on resistive switching of silver programmable metallization cells with GdxOy/AlxOy solid electrolytes

This study investigated the effects of the bottom electrode (BE) on the resistive switching (RS) of silver programmable metallization cells (Ag-PMCs) with gadolinium oxide and aluminum oxide (GdxOy/AlxOy) solid electrolytes (SEs). The RS mechanisms of memories with different bottom electrodes were proposed based on the temperature dependence of the resistance at low resistance state (LRS) and current–voltage (I–V) fitting at high resistance state (HRS). The Schottky emission was dominant in the resistive switching of the memory with an iridium bottom electrode (Ir-BE), whereas in the memories with n+-Si and nickel (Ni) bottom electrodes, silver and both silver and nickel ions dominated the resistive switching, respectively. Additionally, the Ag-PMC with Ni-BE had a high resistance ratio of more than 107 as a result of the extremely low resistance of roughly 50 Ω at LRS. The Ag-PMCs with GdxOy/AlxOy SEs and Ni-BE exhibited a retention behavior of more than 104 s and an endurance of more than 500 cycles with a resistance ratio of at least four orders of magnitude, which is promising for future high-density nonvolatile memory applications.

Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array

The 3-D integration of resistive switching random access memory (RRAM) array is attractive for low-cost and high-density nonvolatile memory application. In this paper, the design tradeoffs of select transistor drivability, RRAM device characteristics, such as switching current ( $I_{W}$ ), on / off -state resistance ( $R_{{\mathrm{\scriptscriptstyle ON}}}$ / $R_{{\mathrm{\scriptscriptstyle OFF}}}$ ), and $I$ – $V$ nonlinearity ratio, interconnect material, and write/read scheme are systematically analyzed using a 3-D circuit simulation. The simulation results show that insufficient current drivability of the vertical transistor severely limits the number of 3-D layers. A low switching current (high $R_{{\mathrm{\scriptscriptstyle ON}}}$ ) or a high nonlinearity is beneficial for improving the write margin, while it degrades the read current sense margin. To alleviate this conflict, the read voltage needs to be boosted to the half write voltage. The common RRAM electrode material TiN is not suitable for the interconnect material due to a high resistivity. To improve write energy efficiency, a multiple-bit write scheme is proposed to reduce the write energy consumption per bit and enable a high bandwidth. With $R_{{\mathrm{\scriptscriptstyle ON}}}=500~\text{k}\Omega $ ( $I_{W}=6~\mu \text{A}$ ) and nonlinearity ratio $=10$ , 1-Mb 3-D vertical RRAM subarray is feasible to meet the specified write/read margin with $\sim 2$ -pJ/bit energy consumption.

(Invited) Scaled Magnetic Tunnel Junctions for High-Density Nonvolatile Memories

We report scaled magnetic tunnel junction (MTJ) for high-density nonvolatile cache memory. Under the same clock frequency, CPU performance can be improved by increasing its embedded cache memory capacity because the probability of cache misses decreases as cache memory capacity increases. Our motivation is to realize small magnetic tunnel junctions which enable high density embedded STT-MRAM cache. We have already proposed a unique fabrication technique which we call it as “shrink process” for reducing the size of a MTJ and realized MTJs with 20 nm in diameter [2014 Symposium on VLSI Technol. pp.212-213].In this paper, in order to realize scaled MTJs with an MgO barrier, two major issues have to be solved. One is to realize a very thin barrier to keep moderate MTJ resistance from the point of a 1-transistor and 1-MTJ memory cell configuration. Another is to fabricate small MTJs without increasing their size variation. In this paper, in order to realize the thin MgO barrier, its leakage mechanism was studied precisely, and proposed its model and possible solutions which will leads to much reduced leakage current and enough write endurance. The shrink process for small MTJs was also investigated from the point of scalability without increasing MTJ size variation. After the MTJ etching, various plasma treatments were done. During this treatment, the sidewall surface of the MTJ was modified, which resulted in the small electrical MTJ size of around 20 nm. Proposed techniques are scalable and promising for sub-20 nm MTJ generations. This work was funded by ImPACT Program of Council for Science, Technology and Innovation.

Thermally Assisted Spin Torque Switching in Magnetic Random Access Memory

Magnetic random access memory (MRAM) consisting of magnetic tunnel junctions (MTJs) is a fascinating candidate for high-density nonvolatile memory. An MTJ has two ferromagnetic metals called free and pinned layers separated by nonmagnetic spacer. The free layer in the MTJ shows two energetically stable states corresponding to the parallel and antiparallel alignments of the magnetizations. These magnetization alignments are distinguished by tunnel magnetoresistance (TMR) effect, i.e., the resistance at the antiparallel alignment is higher than that at the parallel alignment. The free layer is switched between these two stable states by spin torque effect [1], where the transfer of the spin angular momentum from the conducting electrons to the free layer excites the spin torque and induces the magnetization dynamics. The observation of the high TMR ratio more than 100% in CoFeB/MgO-based MTJ [2] has motivated both experimental and theoretical researchers to develop practical MRAM. The free layer should stay one of the stable states to keep information in MRAM. Unfortunately, however, the thermal fluctuation induces probabilistic switching of MTJ. Therefore, high thermal stability is required to guarantee the MRAM performance. Thermal stability of the MTJ is defined by the energy barrier of the free layer separating the two stable states divided by the thermal energy, k B T. Since the retention time of MRAM is exponentially proportional to the thermal stability, a small error in the evaluation of the thermal stability affects the estimation of the retention time significantly. Thus, an accurate evaluation of the thermal stability is necessary. The thermal stability has been evaluated by analyzing the switching probability of the free layer’s magnetization in the thermally activated region assisted by the spin torque. The fitting function of the switching probability is P=1-exp[-ft exp[-Δ(1-I/I c) b ]], where f, Δ, I, and I c are the attempt frequency, thermal stability, current, and switching current at zero temperature, respectively. The switching exponent, b, is assumed to be one [3]. In this study, we study the thermally assisted spin torque switching in an in-plane magnetized MTJ theoretically. The theoretical formula of the switching probability is derived from the Fokker-Planck equation. We find that the switching exponent is larger than one and depends on the applied electric current. The assumption that the switching exponent is one used in previous works is approximately valid only near the low current region, while relatively large current is applied in experiments to obtain the switching probability efficiently. In the high current region, the switching exponent is almost two. We also perform the numerical simulation of the Landau-Lifshitz-Gilbert (LLG) equation with stochastic torque. Figure 1(a) shows the dependence of the probability density, dP/dt, on the current pulse time for several temperatures. As shown, the probability density shows a peak at certain time. We call this time the switching time. Figure 1(b) shows the temperature dependence of the switching time on the temperature. It should be noted that the curvature of the switching time reflects the switching exponent [4]. The nonlinear dependence of the switching time is another evidence that the switching exponent is larger than one. The fact that the switching exponent is larger than one indicates that the previous works have underestimated the thermal stability. The presented formula enables us to evaluate the thermal stability with high accuracy. We also notice that the switching current at zero temperature, I c, can also be evaluated from the switching probability and our formula. We will talk the details of the theoretical analysis of the switching probability and numerical simulation. A comparison with latest experiments will also be presented. (Figure caption) Figure 1: (a) The dependence of the switching probability density on the current pulse time for several temperatures. (b) The temperature dependence of the switching time. [1] J. C. Slonczewski, J. Magn. Magn. Mater. 159, L1 (1996). [2] S. Yuasa, T. Nagahama, A. Fukushima, Y. Suzuki, and K. Ando, Nat. Mater. 3, 868 (2004). S. S. P. Parkin, C. Kaiser, A. Panchula, P. M. Rice, B. Hughes, M. Samant, and S.-H. Yang, ibid 3, 862 (2004). [3] R. H. Koch, J. A. Katine, and J. Z. Sun, Phys. Rev. Lett. 92, 088302 (2004). [4] T. Taniguchi and H. Imamura, J. Nanosci. Nanotechnol. 12, 7520 (2012). T. Taniguchi, M. Shibata, M. Marthaler, Y. Utsumi, and H. Imamura, Appl. Phys. Express 5, 063009 (2012). Figure 1