(Invited) Scaled Magnetic Tunnel Junctions for High-Density Nonvolatile Memories

Abstract

We report scaled magnetic tunnel junction (MTJ) for high-density nonvolatile cache memory. Under the same clock frequency, CPU performance can be improved by increasing its embedded cache memory capacity because the probability of cache misses decreases as cache memory capacity increases. Our motivation is to realize small magnetic tunnel junctions which enable high density embedded STT-MRAM cache. We have already proposed a unique fabrication technique which we call it as “shrink process” for reducing the size of a MTJ and realized MTJs with 20 nm in diameter [2014 Symposium on VLSI Technol. pp.212-213].In this paper, in order to realize scaled MTJs with an MgO barrier, two major issues have to be solved. One is to realize a very thin barrier to keep moderate MTJ resistance from the point of a 1-transistor and 1-MTJ memory cell configuration. Another is to fabricate small MTJs without increasing their size variation. In this paper, in order to realize the thin MgO barrier, its leakage mechanism was studied precisely, and proposed its model and possible solutions which will leads to much reduced leakage current and enough write endurance. The shrink process for small MTJs was also investigated from the point of scalability without increasing MTJ size variation. After the MTJ etching, various plasma treatments were done. During this treatment, the sidewall surface of the MTJ was modified, which resulted in the small electrical MTJ size of around 20 nm. Proposed techniques are scalable and promising for sub-20 nm MTJ generations. This work was funded by ImPACT Program of Council for Science, Technology and Innovation.