Abstract

Spin Transfer Torque Nano-Oscillators (STNOs) and Spin Transfer Torque Magnetic Memories (STT-MRAM) are the two best examples of Spintronic devices exploring the spin transfer mechanism with a strong position to reach real world commercial applications. However, practical applications have requirements where the performance of STNOs is still not good enough. The most notable of these are the need for a larger output power (Pout ∼ 1 μW is required) and narrow line-widths (Γ < 1 MHz). Among the many different implementations of STNOs, those based in Magnetic Tunnel Junctions (MTJs) look the most likely to provide large output oscillations thanks to the large tunneling magnetoresistance effect obtained in CoFeB/MgO/CoFeB stacks. On the other hand, the insulating barriers are prone to dielectric breakdown and the excitation of collective spin dynamics in the ferromagnetic layers require large current densities to be applied and sustained over time (unlike STT-MRAMS which can be switched with current pulses). Therefore, the tunnel barrier endurance to large currents/voltages is a key success factor for the implementation of MTJ based STNOs which is usually met by employing ultra-thin MgO barriers with RxA∼1 Ωμm2. Such thin barriers can sustain large current densities, but they also have a large quantity of defects which result in smaller TMR, lower breakdown and an overall decrease in reliability and reproducibility. In this work, a MTJ stack incorporating a MgO wedge over an 8 inch wafer was deposited with the purpose of clarifying the tradeoffs between endurance to large currents and reliability in ultra-thin and thin MgO barriers. The deposition of the stack (5 Ta / 50 CuN / 10 Ru / 50 CuN / 20 Ru / 17 PtMn / 2 CoFe30 / 0.85 Ru / 2.6 CoFe40B20 / MgO wedge / 2 CoFe40B20 / 10 Ru / 150 Cu / 30 Ru; thickness in nm) was performed using a TIMARIS PVD system with a base pressure of 2.0×10−9 mbar. The MgO wedge structure provides a variable RxA ranging from ∼ 50 Ωμm2 to below 1 across the wafer which was measured in the bulk wafer using a Current-In-Plane-Tunneling (CIPT) technique upon deposition and prior to any process besides annealing. Circular devices with diameters of 200 nm were then fabricated, using a combination of e-beam lithography and ion milling steps which include an ion beam dry planarization step used to expose the top of the pillar upon insulating the bottom contact.

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