High-density Nonvolatile Memory Research Articles

Effects of bottom electrode on resistive switching of silver programmable metallization cells with GdxOy/AlxOy solid electrolytes

This study investigated the effects of the bottom electrode (BE) on the resistive switching (RS) of silver programmable metallization cells (Ag-PMCs) with gadolinium oxide and aluminum oxide (GdxOy/AlxOy) solid electrolytes (SEs). The RS mechanisms of memories with different bottom electrodes were proposed based on the temperature dependence of the resistance at low resistance state (LRS) and current–voltage (I–V) fitting at high resistance state (HRS). The Schottky emission was dominant in the resistive switching of the memory with an iridium bottom electrode (Ir-BE), whereas in the memories with n+-Si and nickel (Ni) bottom electrodes, silver and both silver and nickel ions dominated the resistive switching, respectively. Additionally, the Ag-PMC with Ni-BE had a high resistance ratio of more than 107 as a result of the extremely low resistance of roughly 50 Ω at LRS. The Ag-PMCs with GdxOy/AlxOy SEs and Ni-BE exhibited a retention behavior of more than 104 s and an endurance of more than 500 cycles with a resistance ratio of at least four orders of magnitude, which is promising for future high-density nonvolatile memory applications.

Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array

The 3-D integration of resistive switching random access memory (RRAM) array is attractive for low-cost and high-density nonvolatile memory application. In this paper, the design tradeoffs of select transistor drivability, RRAM device characteristics, such as switching current ( $I_{W}$ ), on / off -state resistance ( $R_{{\mathrm{\scriptscriptstyle ON}}}$ / $R_{{\mathrm{\scriptscriptstyle OFF}}}$ ), and $I$ – $V$ nonlinearity ratio, interconnect material, and write/read scheme are systematically analyzed using a 3-D circuit simulation. The simulation results show that insufficient current drivability of the vertical transistor severely limits the number of 3-D layers. A low switching current (high $R_{{\mathrm{\scriptscriptstyle ON}}}$ ) or a high nonlinearity is beneficial for improving the write margin, while it degrades the read current sense margin. To alleviate this conflict, the read voltage needs to be boosted to the half write voltage. The common RRAM electrode material TiN is not suitable for the interconnect material due to a high resistivity. To improve write energy efficiency, a multiple-bit write scheme is proposed to reduce the write energy consumption per bit and enable a high bandwidth. With $R_{{\mathrm{\scriptscriptstyle ON}}}=500~\text{k}\Omega $ ( $I_{W}=6~\mu \text{A}$ ) and nonlinearity ratio $=10$ , 1-Mb 3-D vertical RRAM subarray is feasible to meet the specified write/read margin with $\sim 2$ -pJ/bit energy consumption.

(Invited) Scaled Magnetic Tunnel Junctions for High-Density Nonvolatile Memories

We report scaled magnetic tunnel junction (MTJ) for high-density nonvolatile cache memory. Under the same clock frequency, CPU performance can be improved by increasing its embedded cache memory capacity because the probability of cache misses decreases as cache memory capacity increases. Our motivation is to realize small magnetic tunnel junctions which enable high density embedded STT-MRAM cache. We have already proposed a unique fabrication technique which we call it as “shrink process” for reducing the size of a MTJ and realized MTJs with 20 nm in diameter [2014 Symposium on VLSI Technol. pp.212-213].In this paper, in order to realize scaled MTJs with an MgO barrier, two major issues have to be solved. One is to realize a very thin barrier to keep moderate MTJ resistance from the point of a 1-transistor and 1-MTJ memory cell configuration. Another is to fabricate small MTJs without increasing their size variation. In this paper, in order to realize the thin MgO barrier, its leakage mechanism was studied precisely, and proposed its model and possible solutions which will leads to much reduced leakage current and enough write endurance. The shrink process for small MTJs was also investigated from the point of scalability without increasing MTJ size variation. After the MTJ etching, various plasma treatments were done. During this treatment, the sidewall surface of the MTJ was modified, which resulted in the small electrical MTJ size of around 20 nm. Proposed techniques are scalable and promising for sub-20 nm MTJ generations. This work was funded by ImPACT Program of Council for Science, Technology and Innovation.

Thermally Assisted Spin Torque Switching in Magnetic Random Access Memory

Magnetic random access memory (MRAM) consisting of magnetic tunnel junctions (MTJs) is a fascinating candidate for high-density nonvolatile memory. An MTJ has two ferromagnetic metals called free and pinned layers separated by nonmagnetic spacer. The free layer in the MTJ shows two energetically stable states corresponding to the parallel and antiparallel alignments of the magnetizations. These magnetization alignments are distinguished by tunnel magnetoresistance (TMR) effect, i.e., the resistance at the antiparallel alignment is higher than that at the parallel alignment. The free layer is switched between these two stable states by spin torque effect [1], where the transfer of the spin angular momentum from the conducting electrons to the free layer excites the spin torque and induces the magnetization dynamics. The observation of the high TMR ratio more than 100% in CoFeB/MgO-based MTJ [2] has motivated both experimental and theoretical researchers to develop practical MRAM. The free layer should stay one of the stable states to keep information in MRAM. Unfortunately, however, the thermal fluctuation induces probabilistic switching of MTJ. Therefore, high thermal stability is required to guarantee the MRAM performance. Thermal stability of the MTJ is defined by the energy barrier of the free layer separating the two stable states divided by the thermal energy, k B T. Since the retention time of MRAM is exponentially proportional to the thermal stability, a small error in the evaluation of the thermal stability affects the estimation of the retention time significantly. Thus, an accurate evaluation of the thermal stability is necessary. The thermal stability has been evaluated by analyzing the switching probability of the free layer’s magnetization in the thermally activated region assisted by the spin torque. The fitting function of the switching probability is P=1-exp[-ft exp[-Δ(1-I/I c) b ]], where f, Δ, I, and I c are the attempt frequency, thermal stability, current, and switching current at zero temperature, respectively. The switching exponent, b, is assumed to be one [3]. In this study, we study the thermally assisted spin torque switching in an in-plane magnetized MTJ theoretically. The theoretical formula of the switching probability is derived from the Fokker-Planck equation. We find that the switching exponent is larger than one and depends on the applied electric current. The assumption that the switching exponent is one used in previous works is approximately valid only near the low current region, while relatively large current is applied in experiments to obtain the switching probability efficiently. In the high current region, the switching exponent is almost two. We also perform the numerical simulation of the Landau-Lifshitz-Gilbert (LLG) equation with stochastic torque. Figure 1(a) shows the dependence of the probability density, dP/dt, on the current pulse time for several temperatures. As shown, the probability density shows a peak at certain time. We call this time the switching time. Figure 1(b) shows the temperature dependence of the switching time on the temperature. It should be noted that the curvature of the switching time reflects the switching exponent [4]. The nonlinear dependence of the switching time is another evidence that the switching exponent is larger than one. The fact that the switching exponent is larger than one indicates that the previous works have underestimated the thermal stability. The presented formula enables us to evaluate the thermal stability with high accuracy. We also notice that the switching current at zero temperature, I c, can also be evaluated from the switching probability and our formula. We will talk the details of the theoretical analysis of the switching probability and numerical simulation. A comparison with latest experiments will also be presented. (Figure caption) Figure 1: (a) The dependence of the switching probability density on the current pulse time for several temperatures. (b) The temperature dependence of the switching time. [1] J. C. Slonczewski, J. Magn. Magn. Mater. 159, L1 (1996). [2] S. Yuasa, T. Nagahama, A. Fukushima, Y. Suzuki, and K. Ando, Nat. Mater. 3, 868 (2004). S. S. P. Parkin, C. Kaiser, A. Panchula, P. M. Rice, B. Hughes, M. Samant, and S.-H. Yang, ibid 3, 862 (2004). [3] R. H. Koch, J. A. Katine, and J. Z. Sun, Phys. Rev. Lett. 92, 088302 (2004). [4] T. Taniguchi and H. Imamura, J. Nanosci. Nanotechnol. 12, 7520 (2012). T. Taniguchi, M. Shibata, M. Marthaler, Y. Utsumi, and H. Imamura, Appl. Phys. Express 5, 063009 (2012). Figure 1

Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications

Beyond use as high density non-volatile memories, memristors have potential as synaptic components of neuromorphic systems. We investigated the suitability of tantalum oxide (TaOx) transistor-memristor (1T1R) arrays for such applications, particularly the ability to accurately, repeatedly, and rapidly reach arbitrary conductance states. Programming is performed by applying an adaptive pulsed algorithm that utilizes the transistor gate voltage to control the SET switching operation and increase programming speed of the 1T1R cells. We show the capability of programming 64 conductance levels with <0.5% average accuracy using 100 ns pulses and studied the trade-offs between programming speed and programming error. The algorithm is also utilized to program 16 conductance levels on a population of cells in the 1T1R array showing robustness to cell-to-cell variability. In general, the proposed algorithm results in approximately 10× improvement in programming speed over standard algorithms that do not use the transistor gate to control memristor switching. In addition, after only two programming pulses (an initialization pulse followed by a programming pulse), the resulting conductance values are within 12% of the target values in all cases. Finally, endurance of more than 106 cycles is shown through open-loop (single pulses) programming across multiple conductance levels using the optimized gate voltage of the transistor. These results are relevant for applications that require high speed, accurate, and repeatable programming of the cells such as in neural networks and analog data processing.

A review of emerging non-volatile memory (NVM) technologies and applications

This paper will review emerging non-volatile memory (NVM) technologies, with the focus on phase change memory (PCM), spin-transfer-torque random-access-memory (STTRAM), resistive random-access-memory (RRAM), and ferroelectric field-effect-transistor (FeFET) memory. These promising NVM devices are evaluated in terms of their advantages, challenges, and applications. Their performance is compared based on reported parameters of major industrial test chips. Memory selector devices and cell structures are discussed. Changing market trends toward low power (e.g., mobile, IoT) and data-centric applications create opportunities for emerging NVMs. High-performance and low-cost emerging NVMs may simplify memory hierarchy, introduce non-volatility in logic gates and circuits, reduce system power, and enable novel architectures. Storage-class memory (SCM) based on high-density NVMs could fill the performance and density gap between memory and storage. Some unique characteristics of emerging NVMs can be utilized for novel applications beyond the memory space, e.g., neuromorphic computing, hardware security, etc. In the beyond-CMOS era, emerging NVMs have the potential to fulfill more important functions and enable more efficient, intelligent, and secure computing systems.

Memory window engineering of Ta2O5-x oxide-based resistive switches via incorporation of various insulating frames.

Three-dimensional (3D) stackable memory frames, including nano-scaled crossbar arrays, are one of the most reliable building blocks to meet the demand of high-density non-volatile memory electronics. However, their utilization has the disadvantage of introducing issues related to sneak paths, which can negatively impact device performance. We address the enhancement of complementary resistive switching (CRS) features via the incorporation of insulating frames as a generic approach to extend their use; here, a Pt/Ta2O5−x/Ta/Ta2O5−x/Pt frame is chosen as the basic CRS cell. The incorporation of Ta/Ta2O5−x/Ta or Pt/amorphous TaN/Pt insulting frames into the basic CRS cell ensures the appreciably advanced memory features of CRS cells including higher on/off ratios, improved read margins, and increased selectivity without reliability degradation. Experimental observations identified that a suitable insulating frame is crucial for adjusting the abrupt reset events of the switching element, thereby facilitating the enhanced electrical characteristics of CRS cells that are suitable for practical applications.

Correction to Redox-Active Molecular Nanowire Flash Memory for High-Endurance and High-Density Nonvolatile Memory Applications.

Correction to Redox-Active Molecular Nanowire Flash Memory for High-Endurance and High-Density Nonvolatile Memory Applications.

Design of Temperature Control Coolant

Design of Temperature Control Coolant

Interfacial Ion Intermixing Effect on Four-Resistance States in La0.7Sr0.3MnO3/BaTiO3/La0.7Sr0.3MnO3 Multiferroic Tunnel Junctions.

A multiferroic tunnel junction (MFTJ), employing a ferroelectric barrier layer sandwiched between two ferromagnetic layers, presents at least four resistance states in a single memory cell and therefore opens an avenue for the development of the next generation of high-density nonvolatile memory devices. Here, using the all-perovskite-oxide La0.7Sr0.3MnO3/BaTiO3/La0.7Sr0.3MnO3 as a model MFTJ system, we demonstrate asymmetrical Mn-Ti sublattice intermixing at the La0.7Sr0.3MnO3/BaTiO3 interfaces by direct local measurements of the structure and valence, which reveals the relationship between ferroelectric polarization directions and four-resistance states, and the low temperature anomalous tunneling behavior in the MFTJ. These findings emphasize the crucial role of the interfaces in MFTJs and are quite important for understanding the electric transport of MFTJs as well as designing high-density multistates storage devices.

Ferroelectric properties of niobium-doped strontium bismuth tantalate films

The characteristics of ferroelectric thin films of strontium bismuth tantalate (SBT) and niobium-doped strontium bismuth tantalate (SBTN) deposited by radio-frequency (RF) magnetron sputtering on Pt/TiO2/SiO2/Si substrates were investigated. For the formation of the structure of the ferroelectric material, the deposited films were subjected to a subsequent annealing at temperatures of 970–1070 K in an O2 atmosphere. The results of the X-ray diffraction analysis demonstrated that, in contrast to SBT films, in which the Aurivillius phase is formed only at annealing temperatures of 1050–1070 K, the formation of this phase in SBTN films is observed already at a temperature of 970 K. The dependences of the dielectric permittivity, remanent polarization, and coercive force of the SBT and SBTN films on the subsequent annealing conditions were determined. It was found that, upon doping of the SBT films with niobium, the remanent polarization increases by a factor of approximately three, the Curie temperature increases by 50 K, and the dielectric permittivity also increases. It was revealed that, in contrast to the SBT films, the polarization of the SBTN films is observed already at an annealing temperature of approximately 970 K. It was shown that the replacement of SBT films by SBTN films in the manufacture of high-density nonvolatile ferroelectric randomaccess memory (FeRAM) capacitor modules makes it possible to decrease the synthesis temperature from 1070 to 990–1000 K, which improves the compatibility with the planar technology of semiconductor devices. However, it turned out that an increase in the coercive field makes niobium-doped SBT films less attractive for the use in FeRAM.

Novel Molecular Non-Volatile Memory: Application of Redox-Active Molecules

This review briefly describes the development of molecular electronics in the application of non-volatile memory. Molecules, especially redox-active molecules, have become interesting due to their intrinsic redox behavior, which provides an excellent basis for low-power, high-density and high-reliability non-volatile memory applications. Recently, solid-state non-volatile memory devices based on redox-active molecules have been reported, exhibiting fast speed, low operation voltage, excellent endurance and multi-bit storage, outperforming the conventional floating-gate flash memory. Such high performance molecular memory will lead to promising on-chip memory and future portable/wearable electronics applications.

Resistive and New Optical Switching Memory Characteristics Using Thermally Grown Ge0.2Se0.8 Film in Cu/GeSex/W Structure.

It is known that conductive-bridge resistive-random-access-memory (CBRAM) device is very important for future high-density nonvolatile memory as well as logic application. Even though the CBRAM devices using different materials, structures, and switching performance have been reported in Nanoscale Res. Lett., 2015, however, optical switching characteristics by using thermally grown Ge0.2Se0.8 film in Cu/GeSex/W structure are reported for the first time in this study. The Cu/GeSex/W memory devices have low current compliances (CCs) ranging from 1 nA to 500 μA with low voltage of ±1.2 V, high resistance ratio of approximately 103, stable endurance of >200 cycles, and good data retention of >7 × 103 s at 85 °C. Multi-steps of RESET phenomena and evolution of Cu filaments’ shape under CCs ranging from 1 nA to 500 μA have been discussed. Under external white-light illumination with an intensity of 2.68 mW/cm2 (wavelength ranges from 390 to 700 nm), memory device shows optical switching with long read pulse endurance of >105 cycles. This CBRAM device has optically programmed and electrically erased, which can open up a new area of research field for future application.

3-D Resistive Memory Arrays: From Intrinsic Switching Behaviors to Optimization Guidelines

3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A systematic study on the intrinsic switching behaviors and optimization of 3-D RRAM arrays is performed, combining device measurements and 3-D array simulations. The dependence of programming voltage on array size, cell location and pulse parameters, statistical properties of operating 3-D RRAM arrays, and subthreshold disturbance on RRAM cells is experimentally investigated. Optimization guidelines for the performance and reliability of 3-D RRAM arrays from device level to architecture level are presented: 1) an optimized 1/ $n$ architecture for 100-kb 3-D RRAM arrays can improve write margin by 69.6% and reduce energy consumption by 75.6% compared with a conventional full-size array design; 2) a strategy of prioritizing storage location for reliable operation is presented; and 3) an optimal hopping barrier of oxygen ions is found to improve array immunity to disturbance.

(Invited) Novel Selector and 3D RRAM Development for High Density Non-Volatile Memory

The development of a higher density non-volatile memory with the 3D vertical resistive random access memory (VRRAM) has attracted great interest from the memory industry. However, VRRAM currently faces the challenges in selecting the specific cell due to a large number of leakage paths, and fabrication process difficulties. In order to eliminate the sneak path and reduce the power consumption, we have developed a novel selector, which shows nearly ideal selector performances with >107 on/off ratio, 0.2 V holding voltage, 10 pA off-state leakage current, sharp on-switch slope of 7 mV/dec, <10 ns turn on speed, >109 endurance, >1.6 MA/cm2 on current density. To investigate the VRRAM performance, we have developed a process flow to fabricate VRRAM and demonstrated a single level sidewall TaOx based VRRAM device. Beside the novel selector and VRRAM integration investigation, we have also proposed a transistor-based novel VRRAM (TB-RRAM) architecture.

All oxide semiconductor-based bidirectional vertical p-n-p selectors for 3D stackable crossbar-array electronics.

Three-dimensional (3D) stackable memory devices including nano-scaled crossbar array are central for the realization of high-density non-volatile memory electronics. However, an essential sneak path issue affecting device performance in crossbar array remains a bottleneck and a grand challenge. Therefore, a suitable bidirectional selector as a two-way switch is required to facilitate a major breakthrough in the 3D crossbar array memory devices. Here, we show the excellent selectivity of all oxide p-/n-type semiconductor-based p-n-p open-based bipolar junction transistors as selectors in crossbar memory array. We report that bidirectional nonlinear characteristics of oxide p-n-p junctions can be highly enhanced by manipulating p-/n-type oxide semiconductor characteristics. We also propose an associated Zener tunneling mechanism that explains the unique features of our p-n-p selector. Our experimental findings are further extended to confirm the profound functionality of oxide p-n-p selectors integrated with several bipolar resistive switching memory elements working as storage nodes.

Self-consistent modelling of electrochemical strain microscopy in mixed ionic-electronic conductors: Nonlinear and dynamic regimes

The frequency dependent Electrochemical Strain Microscopy (ESM) response of mixed ionic-electronic conductors is analyzed within the framework of Fermi-Dirac statistics and the Vegard law, accounting for steric effects from mobile donors. The emergence of dynamic charge waves and nonlinear deformation of the surface in response to bias applied to the tip-surface junction is numerically explored. The 2D maps of the strain and concentration distributions across the mixed ionic-electronic conductor and bias-induced surface displacements are calculated. The obtained numerical results can be applied to quantify the ESM response of Li-based solid electrolytes, materials with resistive switching, and electroactive ferroelectric polymers, which are of potential interest for flexible and high-density non-volatile memory devices.

Novel device structure for phase change memory toward low-current operation

We present a novel device architecture for low set and reset currents in phase change random access memory (PCRAM). In this structure, the sidewall of phase-change film is contacted with the vertical heating layer. In particular, to realize a small contact area of under 50 nm2 for low reset current, this structure includes stacked layers consisting of extremely thin phase change material (PCM) and conduction films, the fabrication method of which is proposed. We estimated set and reset currents for the proposed structure by the device simulation method. Here, we confirmed that a contact area of 30 nm2 in this structure, where Ge2Sb2Te5 is used as PCM, provides a reset current of 13.5 µA and a set current of 4 µA, which are promising for the scaling down of PCM. Furthermore, it is confirmed that the thinner PCM in this structure provides less thermal disturbance to the neighboring cell. From the results, we expect this structure to be a promising candidate for a high-density nonvolatile memory architecture with PCM.

Multi-bits memory cell using degenerated magnetic states in a synthetic antiferromagnetic reference layer

We newly developed a magnetic memory cell having multi-bit function. The memory cell composed of a perpendicularly magnetized magnetic tunnel junction (MB-pMTJ) and a synthetic antiferromagnetic reference layer. The multi-bit function is realized by combining the freedom of states of the magnetic free layer and that in the antiferromagnetically coupled reference layer. The structure of the reference layer is (FeB/Ta/[Co/Pt]3)/Ru/([Co/Pt]6); the top and the bottom layers are coupled through Ru layer where the reference layer has two degrees of freedom of a head-to-head and a bottom-to-bottom magnetic configuration. A four-state memory cell is realized by combination of both degrees of freedom.The states in the reference layer however is hardly detected by the total resistance of MB-pMTJ, because the magnetoresistance effect in the reference layer is negligibly small. That implies that the resistance values for the different states in the reference layer are degenerated. On the other hand, the two different states in the reference layer bring different stray fields to the free layer, which generate two different minor loop with different switching fields.Therefore, the magnetic states in the reference layer can be differentiated by the two-step reading, before and after applying the appropriately pulsed magnetic field which can identify the initial state in the reference layer. This method is similar to distinguishing different magnetic states in an in-plane magnetized spin-valve element. We demonstrated that four different states in the MB-pMTJ can be distinguished by the two-step read-out. The important feature of the two-step reading is a practically large operation margins (large resistance change in reading) which is equal to that of a single MTJ. Even though the two-step reading is a destructive method by which 50% of the magnetic state is changed, this MB-pMTJ is promising for high density non-volatile memory cell with a minor cost of operation speed.

(Invited) Novel Selector and 3D RRAM Development for High Density Non-Volatile Memory

The development of a higher density non-volatile memory with the 3D vertical resistive random access memory (VRRAM) has attracted great interest from the industries. However, VRRAM currently faces the challenges in selecting the specific cell due to a large number of leakage paths, and fabrication process difficulties. In order to eliminate the sneak path and reduce the power consumption, we have developed a novel selector based on doped chalcogenide material. This novel selector shows nearly ideal selector performances with >107 on/off ratio, 0.2 V holding voltage, 10 pA off-state leakage current, sharp on-switch slope of 7 mV/dec, <10 ns turn on speed, >109 endurance, >1.6 MA/cm2 on current density. To investigate the VRRAM fabrication process, we have developed a process flow to fabricate VRRAM and demonstrated a single level sidewall TaOx based VRRAM device. These VRRAM devices can work properly and its switching performance is independent on the thickness of the switching material. Beside the novel selector and VRRAM integration investigation, we have also proposed a transistor-based novel VRRAM (TB-RRAM) architecture. By forming the RRAM cells and transistors at different layer simultaneously, the fabrication cost related to the lithography, etch and deposition can be greatly reduced. Furthermore, with transistor as RRAM selector, better read/write endurance and reliability is expected and it is believed to be industry friendly because of the similar architecture of 3D NAND.