High Density Interconnect Research Articles

(Invited) Pixel-Parallel 3-D Integrated CMOS Image Sensors for Next-Generation Video Systems

We report 3-D integrated CMOS image sensors with pixel-parallel A/D converters (ADCs). Direct bonding of silicon-on-insulator (SOI) wafers with gold electrodes embedded in a SiO2 surface achieves high-density pixel-wise interconnection in the sensor. Prototype 128 × 96 resolution sensors are developed on two SOI wafers with 16-bit ADCs for pulse frequency output integrated in every pixel. We have confirmed successful operation of capturing video images of 16-bit digital output and a wide dynamic range of 96 dB, demonstrating this type of 3-D integration provides functional diversification including circuits, sensors, and More-than-Moore type devices.

Crosstalk noise minimization in novel through silicon via structures

In recent trends, through silicon via (TSV) is essential Technologies for 3-D IC integration because of its short interconnects length and high interconnect density. Beyond the existing structure of TSV, this paper provides a novel structure to investigate the crosstalk effect and same is simulated by using a SPICE simulator and 3-D field solver. The structure of the TSV comprises of copper surrounding by insulating liner, and silicon substrate. In existing structures, silicon dioxide (Sio2) is used as insulating liner because of its material compatibility with silicon substrate. Several researches provide the problem of using Sio2 is due to its high dielectric constant; as a consequence delay will increase. Therefore, Sio2 is not appropriate for high performance applications. In this work, a novel TSV structure is reported to improve the TSV performance which uses poly-propylene polymer liner instead of oxide liner. Signal TSV is enclosed by using a poly-propylene liner and amid the analysis with doping region is created around the ground TSV. For comparison purposes, conventional and proposed TSV structures are simulated. The proposed TSV’s structure simulation results in 30% decrease in crosstalk over existing TSV structures.

A 25.78-Gbit/s × 4-ch Active Optical Cable with Ultra-Compact Form Factor for High-Density Optical Interconnects

A 25.78-Gbit/s × 4-ch active optical cable (AOC) with an ultra-compact form factor is proposed. The size of the proposed AOC is 5.2 cm3, which is 55% smaller than the standard form factor of Quad Small Form-factor Pluggable (QSFP28), and 45% smaller than that of Micro Quad Small Form-factor Pluggable (μQSFP). As a result of utilizing a high-efficiency heat-dissipation structure and optimizing signal transmission lines and ground vias, the proposed AOC achieves high-heat dissipation and low-crosstalk characteristics. Furthermore, the proposed AOC demonstrated 25.78-Gbit/s error-free optical transmission over a 100-m Optical Multimode 3 (OM3) multimode fiber under all-channels (4-ch) operation and case temperature (Tc) of 70 °C.

>1.3-Tb/s VCSEL-Based On-Board Parallel-Optical Transceiver Module for High-Density Optical Interconnects

This paper gives a detailed description of a >1.3-Tb/s VCSEL-based on-board parallel-optical transceiver module for high-density optical interconnects. The optical module integrates a 28-Gb/s × 24-channel transmitter and receiver into one package with a 1-in2 footprint, thereby yielding a data rate density as high as 1.34 Tb/s/in2. A unique module design is developed to utilize the whole top surface for thermal dissipation and the bottom surface for optical and electrical interfaces. The heat dissipation characteristics are studied in simulations and experiments. A test system of 24-channel optical loop-back link is built to evaluate the performance when operating all 24 channels by 28.05-Gb/s 231–1 PRBS bit streams simultaneously. With a total power consumption of 9.1 W, the optical module can be operated within the operating case temperature under a practical air cooling condition. When operating all 24 channels simultaneously, a total jitter margin at BER of 10–12 is larger than 0.4 U.I. at a monitor channel. The measured jitter margin is consistent regardless of any channel operation.

Laminated NbTi-on-Kapton Microstrip Cables for Flexible Sub-Kelvin RF Electronics

Large arrays of superconducting devices such as microwave kinetic inductance detectors require high density interconnects from higher temperatures with minimal heat load, low loss, and negligible crosstalk capable of carrying large and overlapping bandwidth signals. We report the fabrication of superconducting 53 wt% Nb-47 wt% Ti (Nb-47Ti) microstrip transmission lines laminated onto flexible polyimide substrates with lengths up to 40 cm and up to ten traces. The 50 Ω traces terminate in G3PO coaxial push-on connectors. We found transmission losses of 2.5 dB and a nearest-neighbor forward crosstalk of -25 dB at 8 GHz on a typical 5 trace, 1.8-cm-wide, 0.198-mm-thick, 22-cm-long flex cable at 30 mK. A simple two-port analytical model and subsequent Sonnet simulations indicate that this loss is mainly due to a complex impedance mismatch from wirebonds at the end connector without which the insertion loss would be <;2.7 dB/m. This is about six times worse than the transmission measured in Coax Company, Ltd.'s smallest (O 0.86 mm) Nb-47Ti coaxial cables, possibly from differences in the low temperature loss properties of polyimide laminates versus PTFE or from unaccounted resistive losses in the copper adapter coaxes of our tested device. Heat flow calculations from literature data show that the 0.198-mm-thick flex cables tested have roughly equivalent thermal conductance per trace below 4 K compared to the O 0.86 mm Nb-47Ti coaxial cables.

Circular-core single-mode polymer waveguide for high-density and high-speed optical interconnects application at 1550 nm.

We demonstrate circular-core 1550 nm single-mode polymer waveguides with a graded-index profile fabricated by commercially available UV-curable epoxies using so-called mosquito method. The relative index difference ∆n of the waveguides was designed to be 0.46% in order to guarantee both single-mode operation and good compatibility with standard single-mode fiber. Accurate refractive index tuning of monomer for core construction was realized by mixing the core and cladding epoxies properly. The core pitch of the waveguides was chosen to be 50 μm to satisfy the requirements for high-density on-board optical interconnects. Both the optical characteristics and high-speed performances of the waveguides were comprehensively studied at 1550 nm. The measured transmission and coupling loss are 0.79 dB/cm and 0.78 dB, respectively. The waveguides exhibit an inter-channel crosstalk as low as -45 dB, and a 3 dB misalignment tolerance larger than ± 4 μm on the input and output facet in both horizontal and vertical directions. NRZ signal at a data rate of 25 Gb/s was transmitted over a 10 cm-long waveguide. There is no obvious degradation on the eye diagram due to the insertion of the waveguide and error free transmission was successfully obtained. Our results imply that the fabricated single-mode polymer waveguides have good potential in high-density and high-speed optical interconnects application.

Using the SWAT model in analyzing hard rock hydrogeological environments. Application in Naxos Island, Greece.

The main parameter that controls the groundwater flow regime in fractured aquifers is the fracture pattern. Its description is crucial for a hydrogeological study, as the hydraulic properties of hard rocks are mainly controlled by fracturing. The parameters of the fracture pattern that were analyzed in the study area were the frequency and spatial location of the fractures, the density of fractures and the degree of fracture intersection.Furthermore, a straight link between the fracture pattern and the hydrological conditions is important for a first analysis of the potential groundwater zones and their vulnerability in hard rock environments. To study this link, the SWAT hydrology model was applied in the study area. Using suitable territorial and meteorological data, the model simulates the parameters of the hydrological balance in each catchment of the hydrographical network.The analysis of the fracture pattern revealed that the fragmentation in all lithologies is characterized by high degree of uniformity. Very high density and interconnection density of the fractures are observed in areas where the alternations between different lithologies are very intense. Also the application of the SWAT model showed that the calculated hydrological parameters could be related to the fracture pattern, as high infiltration rates occur in areas where the density and the degree of interconnection of the fractures are also high.

TSV-Based 3-D ICs: Design Methods and Tools

Vertically integrated circuits (3-D ICs) may revitalize Moore’s law scaling which has slowed down in recent years. 3-D stacking is an emerging technology that stacks multiple dies vertically to achieve higher transistor density independent of device scaling. They provide high-density vertical interconnects, which can reduce interconnect power and delay. Moreover, 3-D ICs can integrate disparate circuit technologies into a single chip, thereby unlocking new system-on-chip architectures that do not exist in 2-D technology. While 3-D integration could bring new architectural opportunities and significant performance enhancement, new thermal, power delivery, signal integrity and reliability challenges emerge as power consumption grows, and device density increases. Moreover, the significant expansion of CPU design space in 3-D requires new architectural models and methodologies for design space exploration (DSE). New design tools and methods are required to address these 3-D-specific challenges. This keynote paper focuses on the state of the art, ongoing advances and future challenges of 3-D IC design tools and methods. The primary focus of this paper is TSV-based 3-D ICs, although we also discuss recent advances in monolithic 3-D ICs. The objective of this paper is to provide a unified perspective on the fundamental opportunities and challenges posed by 3-D ICs especially from the context of design tools and methods. We also discuss the methodology of co-design to address more complicated and interdependent design problems in 3-D IC, and conclude with a discussion of the remaining challenges and open problems that must be overcome to make 3-D IC technology commercially viable.

Highly Reliable Cu Wiring Layer of 1/1 μm Line/Space Using Newly Designed Insulation Barrier Film

Abstract The interposer or fan-out packaging technology with ultra-fine line/space has been required in order to achieve high density interconnection between chips with low cost. In this paper, we propose the iBF (insulation barrier film) to satisfy the insulation reliability of 1/1 μm ultra-fine trench wiring. The features of iBF are very low moisture absorptivity less than 0.3%, chloride ion impurities less than 1.0 ppm and high resistance to hydrolysis. In addition, iBF has good adhesive strength to Ti and Cu. The trench wiring was fabricated for mechanical and insulation reliability evaluation using photosensitive dielectric, then covered with iBF. The obtained trench wiring with 2/2, 1.5/1.5 and 1/1 μm line/space has passed the reliability tests such as moisture sensitivity level 2, thermal cycling test and biased HAST (highly accelerated stress test). We have also verified high resolution of photosensitive dielectric and fabrication of ultra-fine trench wiring on iBF to realize fine multi-layer wiring.

Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology

Abstract Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technologies to smaller form factor packaging designs with finer line/width spacing as well as improved thermal/electrical performance and the integration of System-in-Package (SiP) or 3D capabilities. SiP technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor as cited above, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called system-on-chip or SoC. As such, SiP incorporates flip chip (FC), wire bond (WB), and fan-out wafer-level packaging (FOWLP) as its technology building blocks and serves various end applications ranging from radio frequency (RF), power amplifiers (PA), Micro-Electro-Mechanical-Systems (MEMS) and Sensors, and connectivity, to more advanced application processors (AP), and other logic devices such as graphics processing units (GPUs)/central processing units (CPUs). FOWLP, also referred to as advanced embedded Wafer Level Ball Grid Array (eWLB) technology, provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D SiP configurations. This paper presents developments in SiP applications with eWLB/Fan-out WLP technology, integration of various functional blocks such as wire bonding, Package-on-Package (PoP), 2.5D, 3D, smaller form factor, embedded passives, multiple redistribution layer routing and z-height reduction. Test vehicles have been designed and fabricated to demonstrate and characterize these low profile and integrated packaging solutions for mobile products including Internet of Things (IoT)/wearable electronics (WE), MEMS and sensors. Finer line/width spacing of 2/2mm with multiple redistribution layers (RDL) are fabricated and implemented on the eWLB platform to enable higher interconnect density and signal routing. Assembly process details, component level reliability, board level reliability and characterization results for eWLB SiP will be discussed.

Under-Bump Metallization Contact Resistance ( $R_{c}$ ) Characterization at 10- $\mu \text{m}$ Polymer Passivation Opening

Under-bump metallization R c is a critical metric for high-density interconnect in electronic devices. We developed a test vehicle to characterize the impact of unit processes on R c for 10- $\mu \text{m}$ polymer passivation opening. We demonstrate that advanced preclean is necessary to achieve low (R c $\text{m}\Omega$ ) for future node extendibility, owing to reduction of both Al oxide and organometallic formation. This is achievable through a combination of low-temperature ( c performance. Influence of SiN etch on R c is also investigated, and it was found that Cl-chemistry is better than F-chemistry to achieve low R c .

High Speed Blind Via Filling By Copper Electrodeposition

Blind vias filling by direct-current copper electroplating is widely used in printed circuit boards (PCBs) to increase input/output (I/O) density due to high density interconnection. The blind vias of a PCB can be filled perfectly by copper electroplating using organic additives such as suppressor, leveler and accelerator in a copper plating bath. However, the current density cannot be raised too high because a void is easily formed at the blind via after filling plating at a high current density. Therefore, this work is to adjust the ratio of organic additives to fill the blind vias of a PCB by copper electroplating at 25℃~30℃ and at a high current density (i.e., 5 A/dm2). The filled blind vias were examined by cross-sectional analysis using an optical microscope (OM) and a scanning electron microscope (SEM). In addition, synergistic effect of organic additives on copper deposition was analyzed by cyclic voltammetry (CV) and linear sweep voltammetry (LSV) to explain how did these additives work for superfilling of the blind via at the high current density.

Fabrication and surface treatment of fine copper lines for HDI printed circuit board with modified full-additive method

PurposeThis paper aims to propose a modified full-additive method (MFAM) to fabricate fine copper lines for high density interconnection (HDI) printed circuit boards (PCBs). In addition, the surface of the fine copper lines is treated with a brown oxidation process to obtain good adhesion between the copper and the dielectric resin.Design/methodology/approachFine copper lines fabricated by MFAM were observed to evaluate the undercut quality, in comparison to undercut quality of copper lines fabricated by the semi-additive method and the subtractive method. The effect of the thickness of the dry film on the quality of the copper plating was investigated to obtain the regular shape of fine lines. The fine copper lines treated with the brown oxidation process were also examined to generate a coarse surface microstructure to improve the adhesion between the copper and the dielectric resin. The cross section and surface of as-fabricated fine copper lines were characterized using an optical microscope, a scanning electron microscope and an atomic force microscope.FindingsMFAM has the potential to fabricate high-performance fine copper lines for HDI PCBs. Undercut of as-fabricated fine copper lines could be prevented to meet the design requirement of impedance. In addition, fine copper lines exhibit enough adhesive force to laminate with dielectric resin after the brown oxidation process.Originality/valueMFAM, with the advantages of high efficiency and being a facile process, is developed to fabricate high-quality fine copper lines for industrial HDI PCB manufacture.

Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes

Monolithic 3-D ICs (M3-D ICs) offer extremely high vertical interconnection density, significantly improving the power-performance envelope when compared to conventional 2-D ICs. However, process limitations lead to one tier having either degraded transistors or interconnects. This paper models the amount of degradation that can be expected at current and future nodes (45, 22, and 10 nm), develops a process development kit using these models to enable evaluation, and presents a block-level M3-D IC RTL-to-GDSII flow that is capable of mitigating some of this degradation. Experimental results indicate that at lower technology nodes, M3-D ICs offer more benefits. Results also indicate that the impact of transistor degradation is diminished at lower technology nodes while the impact of interconnect degradation becomes worse. Overall, perfect M3-D ICs close more than half the gap in the power-performance envelope between 2-D ICs and the “ideal” block-level design. While degraded tiers reduce the benefit of M3-D ICs, our degradation-aware floorplanner gives back up to 17% of the loss, and helps to obtain significant overall benefits compared to 2-D ICs.

Fabrication of Circuits on Flexible Substrates Using Conductive SU-8 for Sensing Applications.

This article describes a new low-cost rapid microfabrication technology for high-density interconnects and passive devices on flexible substrates for sensing applications. Silver nanoparticles with an average size of 80 nm were used to create a conductive SU-8 mixture with a concentration of wt 25%. The patterned structures after hard baking have a sheet resistance of 11.17 Ω/☐. This conductive SU-8 was used to pattern planar inductors, capacitors and interconnection lines on flexible Kapton film. The conductive SU-8 structures were used as a seed layer for a subsequent electroplating process to increase the conductivity of the devices. Examples of inductors, resistor-capacitor (RC) and inductor-capacitor (LC) circuits, interconnection lines and a near-field communication (NFC) antenna are presented as a demonstration. As an example of high-resolution miniaturization, we fabricated microinductors having line widths of 5 m. Mechanical bending tests were successful down to a 5 mm radius. To the best of the authors’ knowledge, this is the first report of conductive SU-8 used to fabricate such planar devices and the first on flexible substrates. This is a proof of concept that this fabrication approach can be used as an alternative for microfabrication of planar passive devices on flexible substrates.

Three-dimensional adiabatic quantum-flux-parametron fabricated using a double-active-layered niobium process

Adiabatic quantum-flux-parametron (AQFP) is an ultra-low-power superconductor logic. In this study, we proposed and designed three-dimensional (3D) AQFP to achieve high circuit density and efficient interconnections. In 3D-AQFP, different AQFP logic circuits can be designed both over and under a ground plane (GP). The 3D-AQFP circuits are fabricated using the AIST 10 kA cm−2 Nb double gate process, in which two active layers are separated by a single GP. Followed by basic logic cell tests, we show an experimental demonstration of a 3D-XOR gate, the building block cells of which are vertically stacked to save circuit area and wiring length. The measurement results showed reasonable excitation current margins of more than ±16% for the 3D-XOR gate.

ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles

Interposer-based 2.5-D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents two efficient ExTest scheduling strategies that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. These strategies target two different ways in which SoC dies are wrapped in 2.5-D ICs. The first scheduling approach is aimed at an extremely large SoC in which the wrapper design requires concurrent testing of the interconnects driving the tile under test. The second scheduling approach is applicable to more general wrapper designs that provide more flexibility in terms of the manner in which these interconnects can be tested. In both test strategies, the tiles in the SoC die are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number of output test pins. In addition, two subgroup configuration methods are further proposed to generate subgroups inside each test group. To highlight the effectiveness of the proposed test strategies, we present scheduling and optimization results for two SoC dies for 2.5-D ICs currently in production.

Selective Plating on Flexible Glass and Polymer Substrates with Laser-Drilled Holes

The simultaneous advancement of Moore’s law along with the miniaturization of interconnects towards so-called HDI (high-density interconnect) design rules has led to a significant revitalization of the printed circuit board industry. As semiconductor wafers become increasingly densely patterned, interconnects have shrunk to keep pace. Shorter interconnect distances translate to shorter rise times and decreased voltage drops, such that a synergy has developed between the shrinking of both integrated circuits and their associated circuit boards. Lasers have largely supplanted mechanical drills to produce microvias (via diameters < 150 µm, often <50 µm) because mechanical bits are prone to catastrophic failure when they become sufficiently thin. Specifically, the recent reduction in cost of ultraviolet lasers has seen an upward trend in adoption among high-end PCB and flex circuit manufacturers. Meanwhile, the technology used to pattern metallic traces and plate microvias has not advanced significantly since the 1970s. There are two competing techniques for PCB metallization: the first is a fully subtractive process whereby a copper clad PCB substrate is lithographically masked and then wet-etched, or laser ablated. The second approach is to utilize a semi-additive process whereby a mask is lithographically defined on the substrate and used to restrict metallization as needed. We report a novel technology to perform electroless metal photo-patterning without the need for traditional lithography. A thin-film precursor solution is applied to a flexible non-conductive substrate, dried, exposed to UV light, and developed in an aqueous solution. Only the irradiated areas remain with catalytically active platinum group metals exposed at the surface. The same ultraviolet lasers used to drill vias can now be utilized for laser direct imaging (LDI), eliminating the need for a separate lithography station. This dense, inorganic polymer is on the order of ten nanometers thick, and promotes adhesion of subsequent electroless metal plating while exhibiting excellent thermal stability. A variety of plating chemistries have been applied, including nickel/tungsten alloys, cobalt/tungsten alloys, and copper. This electroless metal photo-patterning technique not only streamlines PCB fabrication, but is separately a core enabling technology for the low-cost and scalable manufacture of virtual/augmented reality displays – which rely heavily on micro-LED devices to shrink pixel dimensions. NANO3D Systems has demonstrated uniform, well defined metal structures on a variety of flexible non-conductive substrates. Adhesion of nickel alloys to glass substrates was measured by pull test to be >65 MPa. Sheet resistance of as-deposited electroless nickel/tungsten alloy was found to be 18.5 Ω/□ and 157 µΩ/cm for an 85 nm thick film. Once electroplated with 1.1 µm of copper, resistances dropped to 31.7 mΩ/□ and 3.4 µΩ/cm respectively. Chemical composition was confirmed via EDX and WDX. Deposit stress of the Ni/Cu stack was measured to be <13 MPa. Non-uniformity of film thickness by optical profilometry was 1.7% for the Ni/Cu stack. Key challenges in plating chemistry, surface functionalization, and exposure processes have been addressed and are ripe for technology transfer to adjacent applications. Figure 1

Design and Demonstration of a 2.5-D Glass Interposer BGA Package for High Bandwidth and Low Cost

Consumer demand for mobile services is expected to grow with the continued proliferation of connected devices including smartphones, wearables, and Internet of things. As a result, high-performance computing systems that support the core network and cloud infrastructures for these connected devices require unprecedented die-to-die bandwidth at low latency. To achieve next-generation performance requirements and to apply to commercial products, fundamental parameters for 2.5-D interposers are considered including: 1) high interconnect density at short interconnect length; 2) low power consumption; and 3) low packaging cost. The 2.5-D glass interposer described in this paper is superior to silicon interposer in cost and electrical performance, and to organic interposer in interconnect density. This paper describes a 2.5-D glass interposer as a ball grid array (BGA) package to achieve high bandwidth at low cost to improve bandwidth per unit watt signal power per unit dollar cost (BWF) compared to both silicon and organic interposers. Due to its high modulus and excellent surface finish, glass affords ultrafine line lithography to form high-density interconnects comparable to silicon, and the process described in this paper goes beyond silicon back-end-of-line processes by implementing a double-side semi-additive process (SAP) at increased copper layer thickness. This thicker metallization results in reduced conductor losses and improved bandwidth per channel compared to silicon. In addition, the low loss tangent of glass reduces dielectric losses in nets requiring through vias including clock distribution and high-speed off-package signals. Availability of glass in thin panel as well as in roll-to-roll formats beyond 500 mm in size reduces packaging cost compared to 300-mm wafer silicon interposer. The focus of this paper is on the integration of three enabling technologies: 1) advanced SAP for high-density redistribution layers (RDLs); 2) excimer laser ablation of RDL vias; and 3) fine-pitch thermocompression bonding with copper pillar die assembly—for a 2.5-D glass interposer at interconnect densities comparable to that of silicon to achieve terabit per second interdie bandwidth at highest BWF.

Improving wettability of photo-resistive film surface with plasma surface modification for coplanar copper pillar plating of IC substrates

The wettability of the photo-resistive film (PF) surfaces undergoing different pretreatments including the O2CF4 low-pressure plasma (OCLP) and air plasma (AP), is investigated by water contact angle measurement instrument (WCAMI) before the bottom-up copper pillar plating. Chemical groups analysis performed by attenuated total reflectance Fourier transform infrared spectroscopy (ATR-FTIR) and X-ray photoelectron spectra (XPS) shows that after the OCLP and wash treatment, the wettability of PF surface is attenuated, because embedded fluorine and decreased oxygen content both enhance hydrophobicity. Compared with OCLP treatment, the PF surface treatment by non-toxic air plasma displays features of CO, OCO, CO and NO2 by AIR-FTIR and XPS, and a promoted wettability by WCAM. Under the identical electroplating condition, the surface with a better wettability allows electrolyte to spontaneously soak all the places of vias, resulting in improved copper pillar uniformity. Statistical analysis of metallographic data shows that more coplanar and flat copper pillars are achieved with the PF treatment of air plasma. Such modified copper-pillar-plating technology meets the requirement of accurate impedance, the high density interconnection for IC substrates.