High Density Interconnect Research Articles

High-Frequency Ultrasound Array Designed forUltrasound-Guided Breast Biopsy.

This paper describes the development of a miniaturized high-frequency linear array that can be integrated within a core biopsy needle to improve tissue sampling accuracy during breast cancer biopsy procedures. The 64-element linear array has an element width of [Formula: see text], kerf width of [Formula: see text], element length of 1mm, and element thickness of [Formula: see text]. The 2-2 array composite was fabricated using deep reactive ion etching of lead magnesium niobate-lead titanate (PMN-PT) single crystal material. The array composite fabrication process as well as a novel high-density electrical interconnect solution are presented and discussed. Array performance measurements show that the array had a center frequency and fractional bandwidth ([Formula: see text]) of 59.1MHz and 29.4%, respectively. Insertion loss and adjacent element crosstalk at the center frequency were -41.0 and [Formula: see text], respectively. A B-mode image of a tungsten wire target phantom was captured using a synthetic aperture imaging system and the imaging test results demonstrate axial and lateral resolutions of 33.2 and [Formula: see text], respectively.

Advantages and Challenges of 10-Gbps Transmission on High-Density Interconnect Boards

This paper provides a brief introduction to high-density interconnect (HDI) technology and its implementation on printed circuit boards (PCBs). The advantages and challenges of implementing 10-Gbps signal transmission on high-density interconnect boards are discussed in detail. The advantages (e.g., smaller via dimension and via stub removal) and challenges (e.g., crosstalk due to smaller interpair separation) of HDI are studied by analyzing the S-parameter, time-domain reflectometry (TDR), and transmission-line eye diagrams obtained by three-dimensional electromagnetic modeling (3DEM) and two-dimensional electromagnetic modeling (2DEM) using Mentor Graphics HyperLynx and Keysight Advanced Design System (ADS) electronic computer-aided design (ECAD) software. HDI outperforms conventional PCB technology in terms of signal integrity, but proper routing topology should be applied to overcome the challenge posed by crosstalk due to the tight spacing between traces.

A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

This paper presents a robust energy/area-efficient receiver fabricated in a 28-nm CMOS process. The receiver consists of eight data lanes plus one forwarded-clock lane supporting the hypertransport standard for high-density chip-to-chip links. The proposed all-digital clock and data recovery (ADCDR) circuit, which is well suited for today’s CMOS process scaling, enables the receiver to achieve low power and area consumption. The ADCDR can enter into open loop after lock-in to save power and avoid clock dithering phenomenon. Moreover, to compensate the open loop, a phase tracking procedure is proposed to enable the ADCDR to track the phase drift due to the voltage and temperature variations. Furthermore, the all-digital delay-locked loop circuit integrated in the ADCDR can generate accurate multiphase clocks with the proposed calibrated locking algorithm in the presence of process variations. The precise multiphase clocks are essential for the half-rate sampling and Alexander-type phase detecting. Measurement results show that the receiver can operate at a data rate of 6.4 Gbits/s with a bit error rate $ , consuming 7.5-mW per lane (1.2 pJ/bit) under a 0.85 V power supply. With ADCDR’s phase tracking, the receiver performs better in jitter tolerance and achieves a 500-kHz bandwidth, which is high enough to track the phase drift. The receiver core occupies an area of 0.02 mm $^{2}$ per lane.

SiP Technology Trends

System-in-Package (SiP) has become a mainstream package technology of choice by both IC suppliers and OEMs in recent years, and the adoption of package technology is evidenced by the increasing number of devices that utilize this package technology in handsets and mobile segment. However, the adoption of SiP is not limited to only the mobile market, but is also present in IoT, Wearables, as well as in high-end computing market segments. The drivers for adoption of SiP in each market segments, in addition to package technologies suitable within each segment vary. Amongst the many drivers for SiP adoption, the higher integration trend is a common theme across all market tiers as form factor reduction or miniaturization, performance increase, and faster time-to-market are all enabled by such integration schemes. These integration trends impact not only the OSAT's package technologies, but are also impacting the more traditional module assemblies that were historically done at EMS side. The differentiation between OSATs and EMSs become apparent in the level of integration that each can achieve and how their technologies can complement each other in order to collectively provide the highest level of integration possible. The technology blocks used to achieve this higher integration level in 2D packages include the conversion of package design from laminate FC to FOWLP, integration of passives on RDL, and the implementation of IPD's, or in some cases simply through utilization of improved assembly design rules and adoption of more complex process flows. These 2D SiP technologies are well suited for RF devices, and other types of control modules. For 2.5D package configurations, integration scheme is built on the Package-on-Package (PoP) technology framework, and can incorporate both laminate FCPoP as well as FOWLP (eWLB PoP). Here Interposers in combination with micro-bumps and high density interconnects are also used to enable applications in high-end computing. The value-add through such 2.5D technologies, in some cases is the departure from SoC designs with transition to Si partitioning, which yields lower system level cost in advanced nodes, and in other cases is the enhanced performance and form factor reduction that is enabled.

Innovated L/S less than 2/2μm Line Embedded 2.1D Organic Substrate Technology

Current organic substrates are limited to lines/space of 10/10um and via size around 50um. However, the semiconductor with advance node needs fine line/space of 5/5 or 3/3 and even 2/2μm in the future. Si Interposer provides a high density interconnection with fine line and small via that cannot be matched by current laminate substrate technology. But the challenge of Si interposer is the high cost. We have developed an ultra-thin line embedded substrate for 2.1D/2.5D SiP application. There are two types of approach to meet the requirement of line/space less than 2/2μm in the organic substrate. One is the conventional Semi-Additive Process (SAP) and another is laser embedded technology. The advantage of SAP is the good compatibility with current process but the problem is yield and reliability issue for narrow copper trace on the dielectric surface. From the current status, line/space of 5/5μm will be the process limitation of SAP and 2/2μm need to be further verified for HVM. Another solution is line embedded (LE) technology with the different structure. LE technology is different from SAP includes ablation of trench by laser and panel plating with electroplating copper and then removing copper above dielectric surface for formation of Cu pattern. There are several advantages of laser embedded comparing to SAP. First, the laser embedded substrate provides a flat surface after formation of pattern which is helpful for covering a thinner solder mask with better uniformity of thickness. It can avoid the voids formation while filling molding compound. Second, the laser embedded substrate not only allows the design of pad-less via to reduce both package size and format but also can put more traces near these vias. In this study, several key technologies of laser embedded are successfully integrated in the current substrate process. By the selection of the advanced dielectric film with a suitable design as a test vehicle to verify the feasibility of laser embedded technology with line/space of 5/5μm and 3/3μm design. However, the excimer laser ablated the pattern step-by-step and the throughput was much lower than lithography by exposure. The technology trend shows that the use of non-filler photo-sensitive dielectric (PID) by exposure/development to form trenches of signal paths is a good solution to increase throughput. L/S less than 2/2μm line embedded 2.1D organic substrate achievement by adopting innovated integration PID process will be further discussed.

M-Series with Adaptive Patterning for High-Yield Fan-Out SIP

Fan-Out Wafer Level Packaging (FOWLP) holds immediate promise for packaging semiconductor chips with higher interconnect density than the incumbent Wafer Level Chip Scale Packaging (WLCSP). FOWLP enables size and performance capabilities similar to WLCSP, while extending capabilities to include multi-device system-in-packages. FOWLP can support applications that integrate multiple heterogeneously processed die at lower cost than 2.5D silicon interposer technologies. Current industry challenges with die position yield after die placement and molding result in low-density design rules and the high-cost of accurate die placement. Efficiently handling die shift is essential for making FOWLP cost-competitive with other technologies such as FCCSP and QFN. This presentation will provide an overview of Adaptive Patterning, a new technology for overcoming variability of die positions after placement and molding. In this process, an optical scanner is used to measure the true XY position and rotation of each die after panelization. The die measurements are then fed into a proprietary software engine that generates a unique pattern for each package. The resulting patterns are dispatched to a lithography system, which dynamically implements the unique patterns for all packages within a panel. For system-in-packages, this process offers a unique advantage over a fixed pattern: each die shift can be handled independently. With a fixed pattern, the design tolerances need to be large enough for all die to shift in opposing directions, otherwise yield loss in incurred. With Adaptive Patterning, vias and RDL features remain at minimum size and are matched to the measured die shift. The die-to-die interconnects are dynamically generated and account for the unique position of each die. Thus, Adaptive Patterning retains the same high-density design rules regardless of how many die are in a package. Adaptive Patterning provides the capability to use high-throughput die placement to drive down cost, while enabling higher-density system-in-package interconnect. With this technology the industry can finally realize the cost, flexibility, and form factor benefits of FOWLP.

Innovated Process Integration for Panel Size Glass Substrate Manufacturing for SiP Application

Although Silicon interposer has good performance, however high cost is still the major issue and limits its high volume adoption. Therefore to decrease the assembly cost or develop low cost, high density interconnect interposer technology is the keys to enable 2.5D SiP integration. One possibility is to develop low cost interposer by adopting the alternative materials instead of Silicon. The glass, low CTE polymer material, ceramic, etc. may be included. Glass represents an attractive choice with potential of tailorable properties dependent on specific glass composition. By targeting the coefficient of thermal expansion (CTE), the CTE of glass can be made to match perfectly with silicon dies and for reliable package. In addition, the advantages of using glass for interposer derive from process flexibility for size and thickness since the glass fusion process provides sheets with dimensions of more than three meters. It is straight forward to provide glass substrate of almost any size needed. Large glass panels are ideally suited for fabrication of interposer where the panel process is expected to provide large number of interposers in each run compared with wafer processing. Additionally, the two sided processing of the panel, the avoidance of Si wafer CMP processes further enable lower unit cost for the interposer Consequently, glass is an ideal interposer material due to its insulating property, large panel size availability, high modulus and ability to tailor CTE. In this paper, we successfully demonstrate manufacturing feasibility of glass substrate with 4 build-up layers starting with a thin glass panel in 508mm×508mm panel size format and under the IC substrate manufacturing environment. Glass thickness of 100~300um could be processed through the IC substrate HVM line. The laser via in via or direct metallization technology could be selected for double side electrical connection. The copper line width/space of 8/8um was demonstrated by current substrate HVM line. By adopting advanced lithography process and material, line width/space less than 2/2um was achievable. TCT Reliability test without glass crack results will also be discussed.

카본 CCL이 적용된 PCB의 열거동 및 신뢰성 특성 연구

In this paper, the Thermal behavior and reliability characteristics of carbon CCL (Copper Claded Layer), which can be used as the core of HDI (High Density Interconnection) PCB (Printed Circuit Board) are evaluated through experiments and numerical analysis using CAE (Computer Aided Engineering) software. For the characterization of the carbon CCL, it is compared with the conventional FR-4 core and Heavy Cu core. From research results, the deformation amount of the flexure strength of PCB is the highest with pitch grade carbon and thermal behavior of PCB is lowest as temperature increases. In addition, TC (Thermal Cycling), LLTS (Liquid-to-Liquid Thermal Shock) and Humidity tests have been applied in the PCB with carbon core and the reliability of PCB with carbon core is confirmed through reliability tests. Also, possibility of uneven surface of the via hole and wear of the drill bit due to the carbon fibers are analyzed. surface of the via hole is uniform, the surface of the drill bit is smooth. Therefore, it is proved that the carbon CCL has the drilling workability of the same level as conventional core material.

Display glass for low-loss and high-density optical interconnects in electro-optical circuit boards with eight optical layers.

Parallel optical interconnects on-board level requires low propagation loss in wavelength range between 850 and 1550 nm to be compatible with datacom and telecom optical engines. For highest integration density tight waveguide bends and a scalable number of optical layers should be manufacturable for 2D interfaces to optical fiber array connectors and photonic assembly I/O's. We developed a glass waveguide panel process for double-sided processing of commercial available display glass by applying a two-step thermal ion-exchange process for low-loss multi-mode graded-index waveguides. Multiple glass waveguide panels can be embedded between electrical layers. The generic concept enables fabrication of high-density integration (HDI) electro-optical circuit boards (EOCB) with high number of optical and electrical layers. Waveguides with high NA of 0.3 for low bend losses could be achieved in glass with propagation loss of 0.05 dB/cm for all key wavelengths. Four of those glass waveguide panels were embedded in an EOCB demonstrator with size of 280 x 233 mm² providing eight optical layers with 96 channels in an area of 2.8 x 1.5 mm². To the best of our knowledge it's the highest number of layers that has ever been demonstrated for an EOCB.

Effects of Voiding on Thermomechanical Reliability of Copper-Filled Microvias: Modeling and Simulation

The increase in the I/O density and the decrease in the size of electronic packages have driven the need for high-density interconnect (HDI) circuit boards that use microvias as interconnects. One challenge for HDI circuit board development is to fabricate microvias without generating voids in deposited copper structures. A parametric study was conducted to investigate the effects of voids on the thermomechanical reliability of copper-filled stacked microvias using 3-D finite-element analysis and strain-based fatigue life estimation. It was found that microvia fatigue life was affected by geometrical void characteristics, such as shape, size, and location; microvia aspect ratio; and dielectric material properties. While voids are defects in copper-filled microvias, the existence of voids is not always detrimental to microvia reliability. For example, a microvia with a spherical void of 8% volume ratio had a 10% longer fatigue life than the same microvia without voiding. On the other hand, large voids decreased the durability of microvias—a 16% conical void resulted in a microvia fatigue life that was only 1.4% of that of a nonvoided microvia. Moreover, microvia aspect ratio is a critical parameter for reliability. The fatigue life of a voided microvia of 0.25 aspect ratio was more than two orders of magnitude longer than the fatigue life of a voided microvia of 0.75 aspect ratio with the same void volume ratio. As an outgrowth of this study, a microvia virtual qualification method is proposed. Using a combination of finite-element analysis and fatigue life prediction, the required amount of HDI board reliability testing is reduced, cutting overall development time and cost.

L/S ≤ 5/5μm Line Embedded Organic Substrate Manufacturing for 2.1D/2.5D SiP Application

The requirement for IC packages with higher density interconnection with fine line feature has increased significantly recently. Current organic substrates are limited to line/space 8/8μm for Semi-additive Process(SAP), and it will cause yield loss from adhesion issue of line/space less than 5/5μm. But the impact of bad adhesion of fine line is very small in laser embedded (LE) substrate because of its embedded structure. There are several advantages of LE such as the capacity of stereo copper features and better electric performance with lower variation of trench width/depth. It can form fine pitch trench line/space even less than 3/3μm. It also can provide better design flexibility for its pad-less features and better reliability than SAP process. In this paper, we will discuss the key of the processes and demonstrate the fabrication of fine line substrate of 3/3μm line/space by fine tuning line embedded technology. Line embedded trace was made by laser direct ablation (LDA) on organic build-up dielectric material with fine filler size. Laser ablation process capability shows excellent trench depth and shape control. In order to get better copper thickness uniformity, novel uniformity copper plating technology on via, pad and trench has developed. Low cost and uniformity copper reduction process has also been evaluated and developed.

Large Scale Photodesmear for Via Residue Cleaning in High Density Interconnect substrates

Smear residue from the build-up dielectric material is left at the bottom of the microvia after laser drill process which, if not cleaned, poses risk to the electrical functionality of the device. Thus, microvia cleanliness is the key to a reliable and electrically functional device. Currently, industry employs a wet process to clean the etch residue that results in significant chemical waste. Here, we evaluated an alternative, but effective Photodesmear method that provides a low cost of ownership and almost negligible environmental impact. We have demonstrated in IMAPS 2013 that this process can achieve residue- and silica filler free via bottoms by a two-step process: i) illuminating 172 nm vacuum ultraviolet light (VUV) on the panels, resulting in a photochemical ashing, and ii) a water clean. This process does not reduce the surface energy of the build-up material, thus not impacting the downstream processes. The main technical challenge in developing Photodesmear technology will be panel level uniformity in cleaning all the microvias within the same process step. We have demonstrated that our process can achieve a highly uniform treatment over 510 mm wide panels. The process was optimized to clean microvias with a range of aspect ratios on insulating film (material N) drilled by CO2 laser. The microvia bottoms were also found to be clean when the vias were drilled by UV laser to test the desmear capability. The quality of the Photodesmear was tested by measuring the peel strength between electrolytically plated Cu and dielectric surface, and by performing the quick via pull (QVP) to verify the failing interface. We found high peel strength of 0.7 kgf/cm when sputtered Cu seed layer was used. QVP experiments confirmed that the via residue is cleaned effectively since the interface between the plated Cu and the underlying Cu pad did not fail. This study shows that Photodesmear process is capable to produce clean vias along with acceptable peel strength. Future issues are to research the reliability, productivity, and cost of the Photodesmear process to compare with the existing process.

Enhanced optical performance for a reduction stepper to meet the challenges for advanced packaging applications

Mass production of high density interconnects using 3D and 2.5D technologies requires optimal lithography processing with certain optical properties. This paper discusses the modifications and performance changes made to a step-and-repeat camera that have improved the tool utilization. New options are available that enhance the performance and provide the best match to a wide range of resist requirements to attain optimal fidelity and higher throughput. Changes in illumination power, partial coherence and wavelength bandwidth are discussed. Modeling tools are used to predict the improvement and guide the process. Changed optical parameters that impact the image performance are modeled and compared to resist images evaluated. The illumination power increases are used to calculate the impact these changes have on increased throughput. Examples will show modeled and measured improvements achieved.

Multi-criteria optimization in CO2 laser ablation of multimode polymer waveguides

High interconnection density associated with current electronics products poses certain challenges in designing circuit boards. Methods, including laser-assisted microvia drilling and surface mount technologies for example, are being used to minimize the impacts of the problems. However, the bottleneck is significantly pronounced at bit data rates above 10Gbit/s where losses, especially those due to crosstalk, become high. One solution is optical interconnections (OI) based on polymer waveguides. Laser ablation of the optical waveguides is viewed as a very compatible technique with ultraviolet laser sources, such as excimer and UV Nd:YAG lasers, being used due to their photochemical nature and minimal thermal effect when they interact with optical materials. In this paper, the authors demonstrate the application of grey relational analysis to determine the optimized processing parameters concerning fabrication of multimode optical polymer waveguides by using infra-red 10.6µm CO2 laser micromachining to etch acrylate-based photopolymer (Truemode™). CO2 laser micromachining offers a low cost and high speed fabrication route needed for high volume productions as the wavelength of CO2 lasers can couple well with a variety of polymer substrates. Based on the highest grey relational grade, the optimized processing parameters are determined at laser power of 3W and scanning speed of 100mm/s.

Immunity of current-to-voltage transducer, with coils manufactured by means of multilayered PCB technology, to external magnetic fields

Purpose – The purpose of this paper is to discuss the operation of new generation electromagnetic current-to-voltage transducer. The aim of research was analysis of behaviour of considered current-to-voltage transducers during operation. The main problem was to estimate whether the external fields are able to change the value of the secondary voltage and that the replacement of the casing material by a conductive or ferromagnetic material will increase the immunity of the transducer to external magnetic fields. The immunity of current-to-voltage transducers to the external fields is very important because it influences the proper functioning of the protection system. Design/methodology/approach – The use of analytical methods to assess the influence of external fields was impossible due to the complexity of the geometry. The 3D computations were necessary because of different cross sections of circuit boards at different heights. Therefore the numerical 3D field-and-circuit method based on finite element method was applied. The wide range of dimensions in computation system, ranging from 0.15 mm (print paths) to 0.22 m, made it necessary to use the mesh of millions of elements. The division of this type of system into elements requires a diverse and extremely dense mesh in the area of printed circuits board (PCBs). Findings – The 3D analysis of magnetic field distribution was performed for different external field effect upon a current-to-voltage transducer. The magnetic field distributions and the induced secondary voltage for several different cases were presented. As a conclusion it can be said that in this particular case the magnetic shield is most effective. The influence of external magnetic fields caused by currents passing through the other neighbouring phase bars near are insignificant for the transducer with non-magnetic core. Practical implications – Commonly used in measuring and protection systems of the transmission lines are induction instrument transformers. The instrument transformers are very precise devices and their errors are counted in tenths of a per cent, and phase displacement of signals in minutes. Especially in HV systems they are very big and their cores are heavy. Replacement of instrument transformers by the current to voltage transducers cooperating with electronic measuring systems will reduce the size and cost of devices. Originality/value – The requirements set for protective current transformers concern the transformation of currents, with high accuracy, especially at transient states. Therefore magnetic characteristics of their cores should be linear. It causes that cores are large and have some air gaps. Current-to-voltage transducers based on Rogowski coil are particularly suitable for the replacement of the protective current transformers because of their linearity. The traditional technologies used for making Rogowski coil consisted in winding a wire on a non-magnetic carcass. The development of technology has enabled the use of new technologies PCB high density interconnect in the production of Rogowski coil.

Heterogeneous 2.5D integration on through silicon interposer

Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity (<1 mm separation) compared with several centimeters on a typical PCB. In this paper, we have outlined the benefits of adopting 2.5D TSI technology and also highlighted the current day approaches to implement this technology in Si fabrication facilities, and in assembly/packaging factories. While the systems and devices that power the mobile society benefit from exploiting advantages of 2.5D integration on TSI, there do exist surmountable challenges that need to be addressed for this relatively new technology to be used in high volume production of next generation semiconductor devices. The key areas of focus and challenges include: Technology planning and design-execution that are necessary for harnessing 2.5D TSI for building systems, processing flow for the fabrication of 100 μm thick TSI at acceptable costs, manufacturing flow for assembling multiple ICs on a 100 μm thick TSI in a repeatable, and reliable manner, thermo-mechanical analysis and optimization for addressing warpage issues, and thermal management for addressing heat dissipation. We have outlined design, manufacturing methodologies, and challenges, along with solutions to the challenges associated with taking 2.5D TSI technology to high volume production within the next few years.

Microvia and through-Hole Filling By Electroplating for Electronic Circuit Fabrication

Electronic products, such as computers, smart phones, laptops and so on, need chips to perform their functions. These chips have many devices, which need to be integrated and connected with each other. To expand the functions of electronic products, more MOS have not met the requirement yet compared with more chips. Therefore, the concept of three-dimensional (3D) chip stacking packaging is proposed. To meet high density interconnection (HDI), through silicon vias (TSVs), through glass vias (TGVs) used as conducting channels of chip stacking need to be fully filled with metal (e.g., copper or nickel-tungsten alloy), and microvia and through hole designed in IC packaging substrates and printed circuit boards (PCBs) need to be fully filled with copper as well. These filling plating technologies have similar process steps but their feature size is totally different.1-11 Herein, we will review these process steps and propose novel filling plating process steps and technologies, including highly selective microvia filling without copper deposition on the outside plane surface, direct through hole filling without usage of a conducting template, TSV filling using CoWP as a barrier layer and electroless copper as a seed layer, TSV filling using reduced graphene oxide (rGO) as barrier and seed layers, TSV filling without copper but rGO combining with NiW alloy, TGV filling using electroless copper as a seed layer and direct pattern copper electroplating onto a glass wafer by using Al-doped ZnO (AZO) as an adhesive and conducting layer.

Nanowire-Based Anisotropic Conductive Film: A Low Temperature, Ultra-fine Pitch Interconnect Solution

Advanced microelectronics packaging, driven by the multiple benefits of system performance, power, size, and cost, has now entered the three-dimensional (3-D) era. According to the International Technology Roadmap for Semiconductors 2012 [1], the interconnect pitch size is predicted to be 4?16 ?m at the global interconnect level by the year 2018. Silicon die incorporated with through-silicon-via (TSV) technology [2] can be stacked using solder microbumps as high-density interconnects [3]. However, solder microbump technology faces many challenges because of the intermetallic compound growth and an underfill requirement as the bump size reduces [4]. Meanwhile, the temperature of the soldering process is more than 260 ?C, which can result in high thermal stress in the devices and impact the thermal budget of the processing, particularly for the multitechnology node-stacking processes [5]. Therefore, developing interconnect methods, which can provide ultrafine-pitch capability and low-temperature process for 3-D systems, attracts continuous attention from industry [6].

Multiphysics coupling simulation of RDE for PCB manufacturing

Purpose– The purpose of this paper is to optimize experimental parameters and gain further insights into the plating process in the fabrication of high-density interconnections of printed circuit boards (PCBs) by the rotating disc electrode (RDE) model. Via metallization by copper electrodeposition for interconnection of PCBs has become increasingly important. In this metallization technique, copper is directly filled into the vias using special additives. To investigate electrochemical reaction mechanisms of electrodeposition in aqueous solutions, using experiments on an RDE is common practice.Design/methodology/approach– An electrochemical model is presented to describe the kinetics of copper electrodeposition on an RDE, which builds a bridge between the theoretical and experimental study for non-uniform copper electrodeposition in PCB manufacturing. Comsol Multiphysics, a multiphysics simulation platform, is invited to modeling flow field and potential distribution based on a two-dimensional (2D) axisymmetric physical modeling. The flow pattern in the electrolyte is determined by the 2D Navier–Stokes equations. Primary, secondary and tertiary current distributions are performed by the finite element method of multiphysics coupling.Findings– The ion concentration gradient near the cathode and the thickness of the diffusion layer under different rotating velocities are achieved by the finite element method of multiphysics coupling. The calculated concentration and boundary layer thicknesses agree well with those from the theoretical Levich equation. The effect of fluid flow on the current distribution over the electrode surface is also investigated in this model. The results reveal the impact of flow parameters on the current density distribution and thickness of plating layer, which are most concerned in the production of PCBs.Originality/value– By RDE electrochemical model, we build a bridge between the theoretical and experimental study for control of uniformity of plating layer by concentration boundary layer in PCB manufacturing. By means of a multiphysics coupling platform, we can accurately analyze and forecast the characteristic of the entire electrochemical system. These results reveal theoretical connections of current density distribution and plating thickness, with controlled parameters in the plating process to further help us comprehensively understand the mechanism of copper electrodeposition.

Electron backscatter diffraction characterization of electrolytic Cu deposition in the blind-hole structure: Current density effect

Blind-hole (BH) filling via direct-current Cu electrodeposition is widely used in high-density interconnection technology for advanced printed circuit boards (PCBs). In this study, electrolytic Cu BH fillings deposited at various current densities (j=2, 4, 5, and 6A/dm2) were investigated using transmission X-ray microscopy (TXM), field-emission scanning electron microscopy (FE-SEM), and electron backscatter diffraction (EBSD). The TXM, FE-SEM, and EBSD investigations indicated that the Cu deposition morphology (e.g., void formation and concave surface Cu) and its crystallographic microstructure (e.g., orientation and twin structure) were strongly dependent on j. The formation of voids and concave surface Cu in the BH fillings inevitably degraded the thermomechanical and electrical characteristics of the Cu deposition, deteriorating the reliability of PCB Cu interconnection. These dependencies revealed that j is an important factor of the Cu electrodeposition in the BH structure and should be reduced to a level of j<4A/dm2 to avoid the undesired microstructures. This knowledge serves to advance the understanding of the role of the current density in the Cu BH filling process.