High Density Interconnect Research Articles

Process Modules for High-Density Interconnects in Panel-Level Packaging

Advanced packaging technologies like wafer-level fan-out and 3-D system-in-package (3-D SIP) are rapidly penetrating the market of electronic components. For cost reduction, one approach is the migration of processes from wafer to panel format, called panel-level packaging (PLP). In a consortium of partners from industry and research, advanced technologies for PLP are developed. The project aims for an integrated process flow for 3-D SIPs with chips embedded into an organic laminate matrix. At first, 6 mm $\times 6$ mm chips (100 $\mu \text{m}$ thickness) with Cu bumps (25- $\mu \text{m}$ height, 110- $\mu \text{m}$ pitch) are placed into cavities of a printed circuit board (PCB) core layer. They are embedded by vacuum lamination of thin organic films. The core is equipped with fiducials for local alignment and provides handling robustness. Developments aim for a final panel size of 600 mm $\times600$ mm (here 227 mm $\times305$ mm demonstrated). Onto the contact side of embedded chips, a 25- $\mu \text{m}$ dielectric film is applied. The copper bumps are subsequently opened by plasma etching. By sputtering and electroplating of Cu, electrical contacts to the chips are formed without via opening. High-aspect-ratio vias as an element for vertical interconnects are formed by UV laser drilling. At via diameters of 17 $\mu \text{m}$ , a drill hole depth of 74 $\mu \text{m}$ was achieved (aspect ratio 4.4:1). Using a newly developed electrolyte, microvia filling was achieved for aspect ratios up to 4:1. With a newly developed direct imaging (DI) machine, 4- $\mu \text{m}$ structures in a 7- $\mu \text{m}$ dry film photoresist are formed. Adaptive imaging of a redistribution layer was realized.

A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics/CMOS 3D-Integration Platform

With the growing demand for automotive LiDAR and the maturation of silicon photonics platforms, optical phased arrays (OPAs) have emerged as a key technology for solid-state optical beam-steering. In order to meet realistic automotive specifications with OPAs, >500 antenna elements should work reliably under tight power and cost budgets. Existing multi-chip solutions necessitate expensive packaging and assembly to achieve high interconnect density. Even with 2-D monolithic integration, high-voltage drivers to deliver sufficient power to resistive phase shifters typically result in significant overhead in die area and limited power efficiency. In this article, we introduce a single-chip OPA realized through wafer-scale 3-D integration of silicon photonics and CMOS. Flexible and ultra-dense connections with through-oxide vias (TOVs) in our platform resolve the I/O density issue. Moreover, low-voltage L-shaped phase shifters and compact, efficient switch-mode drivers, connected vertically using TOVs, remove wiring/placement overhead and achieve a large active array aperture within a compact die. Our OPA prototype achieves wide-range 2-D steering over 18.5 $^\circ \times $ 16° by leveraging wavelength tuning and phase control, and array scaling up to 125 elements with a large aperture size of $0.5\,\mathrm {mm}\times 0.5\,\mathrm {mm}$ and 0.15 $^\circ \times $ 0.25° beamwidth while consuming 20 mW/element average power. Since our system supports per-element independent phase control, increased sensitivity to process variations in L-shaped shifters is fully compensated by a simple calibration process.

Embedded Multidie Interconnect Bridge—A Localized, High-Density Multichip Packaging Interconnect

This article provides an overview of the embedded multidie interconnect bridge (EMIB) multichip packaging (MCP) technology. EMIB is a unique packaging paradigm that provides very high-density interconnects (currently in the range of 500–1000 I/O/mm) localized in between two devices, thus enabling high-bandwidth (BW) on-package links while leaving the rest of the package structures and designs unaffected. The construction of the silicon bridge and the package to allow high BW electrical signaling between two dies is discussed in detail. Examples of the EMIB implementations for the links between the field-programmable gate array (FPGA) logic and high bandwidth memory generation 2 (HBM2) memory stacks, graphics die and HBM2 memory stacks, FPGA logic die, and high-performance transceiver die are described. EMIB packaging is compared with similar high-density interconnect technologies such as silicon interposer with through-silicon vias (TSVs) and other fan-out-based package technologies. Design optimization strategies for power delivery and I/O routing in the presence of an embedded bridge are highlighted.

Innovative Sub-5-$\mu$ m Microvias by Picosecond UV Laser for Post-Moore Packaging Interconnects

This article presents for the first time microvias scaled down to sub-5 μm in diameter fabricated using picosecond UV laser ablation in a nonphotoimageable dielectric film. The motivation of this article is to address post-Moore and More-than-Moore packaging interconnect needs. Microvias play a critical role in package interconnections in IO density and the IC bump pitch for 2.5-D interposers and fan-out packages. UV laser ablation has been the key technology for fabricating small microvias in high density interconnect (HDI) packaging for more than two decades. The state-of-the-art microvia fabricated by UV laser ablation is still at 20 μm in diameter and 50 μm in pitch. This article explores the feasibility of fabricating microvias of 5 μm or less in diameter with a commercially available picosecond UV laser system. The experimental results show that microvias of 5 μm or less in diameter in a 5-μm-thick Ajinomoto buildup dielectric film (ABF) are achieved. This article also addresses the fundamentals of picosecond pulsed laser ablation on polymer dielectric materials and processes optimization to generate sub-5-μm microvias. The via pitch of 8-12 μm is demonstrated. UV laser ablation also addresses the issue of limited availability of photosensitive dielectric materials for photolithography-based microvia fabrication.

New Thin Adhesive for High Density 2.5D Heterogeneous Device Integration with Cu-Cu Hybrid Bonding

Abstract Heterogeneous integration of logic, memory, and sensor chips on interposers (2.5D) has attracted a lot of attention as a candidate for More-than-Moore technology. For the high performance 2.5D devices, high density integration of chips with narrow spacing and high density interconnections with small pitch bonding electrodes are a key technology. In the current bonding technology, solder micro-bumps (>20 μm in diameter) and non-conductive adhesives have been adopted. There may be some limitations for high density device integration with these technologies because of the protrusion of adhesives around the chips, the thermal sliding at the bonding, and the limit of solder micro-bump minimization. Hybrid bonding with a small Cu electrode (<10 μm in diameter) is a strong candidate for improving advanced device integration technology. Our goal is to develop a new adhesive which gives no protrusion, no thermal sliding, no voids, and high electrical reliability. A spin coating thin adhesive was therefore developed. The new adhesive can be cured at 200 °C. The cured adhesive film has no tackiness and has an optically flat surface. The adhesive film can be temporarily bondable to SiO2 at room temperature. After 200 °C baking, a permanent bonding can be achieved, and there is no degradation of bonding strength and no voids even after 400 °C of baking. For the applicability to the chip-on-wafer process, the adhesive film/Si wafer can be cut into chips by blade dicing without any delamination and without any apparent particles. After bonding the adhesive/Si chip to a bare Si wafer at room temperature, the thermal sliding amount after the thermal compression process (250 °C, 10 min, 1 MPa) was less than 1 μm (under the detection limit) according to optical microscopic measurements. In addition, there was no protrusion of adhesive around the chip corner from SEM. A first trial result for hybrid bonding is also reported.

Non-destructive In-line IMC Thickness Measurement Using Acoustic Metrology for 3D Stacking

Abstract The constant demand for small-feature-size, high performance and dense I/O applications have necessitated the development of fine-pitch vertical interconnects for 3-D integration. Microbumps and through silicon vias enable the high-density vertical interconnects. As microbumps scale, intermetallic compound formation during thermocompression bonding and its impact on reliability is a concern. In this paper, we describe the application of picosecond acoustic metrology technology as a viable option for non-destructive characterization of the intermetallic compounds. The small spot size technology allows measurement on small bumps, with very good accuracy and repeatability.

Nanovoid Formation at Cu/Cu/Cu Interconnections of Blind Microvias: A Field Study

Abstract A key factor for a high electrical reliability of multilayer High Density Interconnection Printed Circuit Boards (HDI PCBs) is the thermomechanical stability of stacked microvia interconnections. With decreasing via sizes and higher numbers of interconnected layers, the structural integrity of these interconnections becomes a critical factor and is a topic of high interest in current research. The formation of nanovoids and inhibited Cu recrystallization across the interfaces are the two main indications of a weak link from the target pad to the filled via. Based on TEM/EDX measurements on a statistically relevant number of stacked and blind microvias produced in the industrial field, different types of nanovoid phenomena are revealed at the Cu/Cu/Cu junction. The types of nanovoids were categorized relating to the time of appearance (before or after thermal treatment), the affected interfaces or layers and the impact on the Cu recrystallization. The main root causes for each void type are identified and the expected impact on the thermomechanical stability of the via junction is discussed.

Reduced Cladding Diameter Fibers for High-Density Optical Interconnects

Data centers are continually striving to meet the challenge of delivering more bandwidth, and this will require higher capacity optical switches and servers. One proposal for achieving this higher bandwidth density is to use embedded optical transceivers, which have arrays of VCSEL or silicon-photonic lasers integrated into on-board and co-packaged optics. The capacities of these transceivers are limited by the densities of the arrays, which in turn depend on the physical dimensions of the optical fibers that are coupled to the chip. This size constraint is motivating component manufacturers to consider using optical fibers with reduced cladding (RC) and coating diameters to enable higher density interconnects. In this paper, we introduce bend-insensitive single-mode and multimode RC fibers that have low attenuation, low bend loss, and are backward-compatible with the installed base of standard optical fibers. We also discuss how these RC fibers can be integrated into fiber array units to create a high-density fiber-chip connectivity solution.

(Invited) Microfluidic Electroless Interconnection (MELI) Process for Low-Temperature, Pressureless Chip Stacking Applications

Increasing demands for high-performance miniaturized electronic devices have driven the semiconductor industry toward finer pitch and higher interconnect density. Copper pillar has been widely adopted and is rapid becoming the mainstream bumping technology for high-density interconnections, such as 2.5D and 3D IC packaging. Thermo-compression bonding has been widely used for high-density copper pillar bumps because of its highly accuracy alignment and placement. However, the high heat and high force applied to the components during the bonding process often induce high thermal-mechanical stress that causes severe damage to the devices and low-k dielectric layers. Because the mechanical properties of porous, low-k materials decreases with lower dielectric constants, this issue will become more severe in the future when lower dielectric constant materials are employed. Therefore, it is imperative to develop a low-temperature, low-pressure bonding process. To address this issue, a novel Cu-to-Cu bonding process called microfluidic electroless interconnection has been developed. This novel process forms electroless metal interconnections as a replacement for solders, which eliminates all the reliability concerns involved with soldering. Specifically, the process is able to bond copper pillars at a low temperature without applied any pressure. The operating temperature of the process is around 80 °C, which is considerably lower than most bonding processes. Also, there is no need to apply any bonding pressure throughout the bonding process due to the proposed bonding scheme structure. In this way, the thermo-mechanical stress can be largely reduced to maintain the structural stability of packaging. Furthermore, the most exciting aspect of this new approach is the integration of microfluidic technology with the electroless plating process, which allows to precise control the flow of fluids in and out the stacked chip to achieve better bonding performance. The flow rate can quantitatively determined and the fluid flow can be adjusted for either batch or continuous-flow operations. The main objective of this work was to investigate the feasibility of the microfluidic electroless interconnection process in joining copper pillars as a promising route for a low-temperature, pressureless bonding process. First, the overall plating uniformity across the entire die surface at different stand-off heights of the stacked chips was investigated. Preliminary results demonstrated that, by selecting a proper flow rate, a high level of plating uniformity across the die was obtained regardless of the standoff heights. In addition to the electrolessly bonded joints, when the bonding interface was examined by scanning electron microscopy (SEM) and focus ion beam (FIB), it was confirmed that no voids or seams appeared on the bonding interface between the pillars, indicating that the two electroless Ni layers that grew on the opposite sides had merged completely into a single structure. The growth and bonding mechanism of the electroless interconnection process was investigated and characterized fully. The bonding interface and phosphorus distribution in the electroless Ni bonds were examined by an electron probe micro-analyzer (EPMA) to ascertain the effect of batch and continuous flow processing. Moreover, the results of direct shear test shows that the bond strength of the electroless Ni between the copper pillars was greater than the adhesion strength of the Cr layer. Further, it was found that the process has the ability to compensate not only for non-uniform copper surfaces, but also for the misalignment and height mismatch of copper pillars, which provides a competitive edge over other bonding methods. This innovative low-temperature, pressureless electroless bonding approach shows considerable promise for applications that require low stress and low thermal budget process.

Advanced Low-K Polymer Dielectric Materials and Interfaces for Fine-Pitch Re-Distribution-Layer (RDL) to Enable 2.5D and Fan-out Packages

The rapid increase of devices with artificial intelligence (AI) and machine learning capabilities is driving the demand for growth in compute performance. With transistor scaling reaching physical limitations, the semiconductor industry is looking to system-scaling to deliver the performance improvements. Advanced packaging architectures capable of supporting these applications are 2.5D interposers, 3D IC stacking, chiplets and fan-out based packaging. All of these architectures require high-density interconnects capable of routing >200 IOs/mm/layer. This talk demonstrates advanced ultra-thin ( <10 µm), low-Dk (< 3.0) polymer dielectric material candidates capable of achieving I/O densities of 500 IOs/mm/layer. Current commercially available solutions based on silicon interposers suffer from conductor and dielectric losses because of restrictions on the dielectric material (SiO2). Polymer based dielectrics offer a compelling alternative because of the potential to reduce the capacitance of the traces and improve power efficiency alongside compatibility with low-cost panel-scalable processes. This idea is explored will be explored in this talk and we will demonstrate through modelling and characterization that low-Dk polymer dielectrics are a superior candidate to current dielectric material candidates The choice of polymer dielectric is driven by technology trends towards a)high-density fine-pitch routing b)system level thermo-mechanical reliability c)panel-scalable processing. This work examines four dielectric material candidates comprising of 3 material classes, namely photo-sensitive epoxy, non-photo-sensitive epoxy and BCB for next-generation interconnect technology. High-speed electrical simulations indicate that low-Dk materials can support data rates of >10Gbps which overcomes the limitations faced by conventional high Dk epoxy dielectrics and SiO2 alternatives. The biggest challenge in moving towards low-Dk materials is that these polymers are typically non-polar and do not adhere well which poses challenges in package integration. This work proposes a unique approach to improve polymer/metal interfacial adhesion by creating a hybrid layer with tailorable material properties using vapor-phase-infiltration (VPI). VPI exposes the polymeric material to a metal-organic reactant such as trimethyl aluminium (TMA) in a heated environment. Diffusional kinetics of the reactant are highly dependent on each step of the sequential process such as temperature, time of hold, exposure time, and co-reactants used. This process is superior compared to Atomic Layer deposition (ALD) in promoting the diffusion of organometallic precursors into the polymer subsurface because of a hold-period after exposure. VPI thereby provides a highly adaptable process to create tunable hybrid interfaces with target properties. VPI-treated polymers showed a 3X improvement in adhesion strength at the polymer/metal interface. This work dives into the kinetic factors required to achieve this adhesion improvement and characterizes the corresponding material structure changes. In summary, advanced low-Dk polymer dielectrics capable of meeting next-generation high-performance computing requirements are discussed. This work evaluates the key performance benefits from moving to low-Dk dielectric materials and tackles a critical challenge of integrating these materials as re-distribution layer (RDL) dielectrics by demonstrating 3X improvement in adhesion using VPI.

Novel high-density interconnection technology for the CBM Silicon Tracking System

In the Silicon Tracking System of the Compressed Baryonic Matter experiment at the future accelerator facility FAIR, double-sided microstrip sensors with sizes up to 62 x 124 mm will be connected to the readout electronics by means of up to 50 cm long lightweight microcables. The well-established aluminum to aluminum TAB bonding technology between die and microcable is highly manual and time-consuming. Therefore, a novel high-density interconnection technology based on a copper-polyimide flex microcable has been developed. It combines gold stud bumping on the die with solder paste printing on the microcable and a flip chip interconnection process. Shear strength and cross-section analysis have been performed on the bonded structures to optimize the solder paste reflow as well as the flip chip bonding process. First underfill application studies have been conducted successfully.

A graphene rheostat for highly durable and stretchable strain sensor

AbstractStrain sensors for human health monitoring are of paramount importance in wearable medical diagnostics and personal health monitoring. Despite extensive studies, strain sensors with both high durability and stretchability are still desired, particularly with the stability for different environmental conditions. Here, we report a series of strain sensors possessing the graphene network with a high density of intermittent physical interconnections, which produces the relative resistance change by varying the overlap area between the neighboring graphene sheets under stretching and releasing, analogous to the slide rheostat working in electronics. Our in‐situ transmission electron microscope observation reveals the full recoverability of the structure from large deformation upon unloading for ensuring the exceptional cycle stability of our material on monitoring full‐range body movements. The stable response is also demonstrated over wide temperature range and frequency range, because the peculiar dynamic structure can be maintained through the self‐adjustment to the thermal expansion of the bulk material. Based on the working mechanism of graphene “slide rheostat,” the sensing properties of the strain sensor are tailored by tuning the graphene network structure with different mass densities using different concentrations of graphene oxide dispersion, while the stretchability and sensitivity can be separately optimized for different application requirements.

Cellular Automata Based Test Design for Coherence Verification in 3D Caches

To provide high vertical interconnection density between device tiers, Through Silicon Via (TSV) offers a promising solution in 3D caches. It reduces the length of global interconnection and ensures high speed cache memory access. Maintaining coherency of shared data in such caches is, however, very crucial and, therefore, demands that the reliability and accuracy of TSVs as well as the cache coherence controller (CC) are to be ensured. In the current work, we propose an elegant test solution for at-speed detection of stuck-at-faults in TSVs (offline test) as well as verification for the functioning of CC (online test). The proposed test structure is designed around the modular and cascadable structure of Cellular Automata (CA) to achieve a cost-effective realization of test and coherence verification in 3D caches with high degree of scalability. It ensures correct decisions in more than 71% cases even if the test hardware is subjected to single stuck-at-fault.

The Formation of Nano-voids in electroless Cu Layers

ABSTRACTThe electrical reliability of multilayer high density interconnection printed circuit boards (HDI-PCBs) is mainly affected by the thermo-mechanical stability of stacked micro via interconnections. Here, a critical failure mode is the stress related crack between the electrolytically filled via and the target pad, commonly known as target pad separation. The junction includes two Cu-Cu-interfaces, one between the target Cu pad and the thin electroless Cu layer and the second between electroless Cu and electrolytic Cu. In this paper we will show that state-of-the-art electroless Cu plating processes are able to provide solid, completely recrystallized and highly reliable stacked via junctions. Defect free interfaces were achieved by using ionic Pd-activators and electroless Cu baths with a cyanide based stabilizer system. Cyanide free electroless Cu baths tend more to the formation of nanometer sized defects, discovered via Transmission Electron Microscopy (TEM). In this case a precise adjustment of single stabilizer components is mandatory to achieve defect free layers. The defects are hollow and were identified as “nano voids”. A critical density of these nano voids weakens the interface, predefines the crack path and reduces the overall reliability of the junction. A precise localization of the nano voids within the junction was enabled by detecting the Ni-containing electroless Cu layer via TEM-Ni mapping. Slower volume exchange of the electroless Cu solution within the blind micro via (BMV) substantially increases the nano void density. The ability of nano voids to migrate and coalesce at elevated temperatures was investigated as well.

Design parameters and environmental impact of printed wiring board manufacture

Abstract The environmental life cycle impact of electronics continues to be of interest within the life cycle arena. Previous work has shown the majority of burden can be attributed to the use phase as well as the manufacturing impact of components. This study leverages primary data from an industrial facility to provide an assessment of the cradle-to-gate global warming potential for printed wiring board (PWBs) components used in electronics equipment. There has not been as much evolution in the technology for PWBs as compared to other components such as integrated circuits. A newer technology, high-density interconnect (HDI) PWBs, is evaluated in addition to conventional boards based on various representative designs for consumer products. The results show that the board impact for handheld devices, notebooks and desktops range from to around 0.6 to 10 kgCO2e/board. The cradle-to-gate global warming potential is dominated by the manufacturing energy to fabricate the board as well as the board laminate materials (80% of the total impact). The study demonstrates that environmental impact varies by design parameters other than layer count and board area. The research also assesses the water use and chemical hazard associated with PWB manufacture.

Directly inscribed multimode polymer waveguide and 3D device for high-speed and high-density optical interconnects.

A 75-cm-long circular-core polymer waveguide compatible with standard 50-μm-core multimode fibers (MMFs) is designed and fabricated by using a direct inscribing method for high-speed and high-density optical interconnects. The fabricated waveguide has low loss (<0.044 dB/cm at 850 nm) and low crosstalk (<-34 dB with a core pitch of 62.5 μm) with a negligible coupling loss with the MMFs. It also exhibits a low bending loss (<0.08 dB/mm with a bending radius of 4 mm), which agrees well with calculated results. Error-free NRZ data transmission over the 75-cm-long waveguide at 25 Gb/s is demonstrated, and 4 × 25 Gb/s short wavelength division multiplexing (SWDM) is realized on a straight waveguide. Moreover, a two-layer waveguide and a 3-dimensional (3D) Y-splitter/combiner are also fabricated for 3D integration.

Spectroscopic Investigation of Complex Redox Equilibria in Cupric Chloride Subtractive Etching for Cu High Density Interconnects

The continuously increasing demand for innovation in the miniaturization of microelectronics has driven the need for ever more precise fabrication strategies for device packaging, especially for printed circuit boards (PCBs). Subtractive copper etching is a fundamental step in this processes, requiring very precise control of etch rate and etch profile. Cu etching baths are typically monitored with several parameters including oxidation-reduction potential, conductivity, and specific gravity. However, the etch rate and etch profile can be difficult to control even under strict engineering controls of those monitoring parameters. The basic understanding of the Cu etching is shown in the figure below [Fig 1], whereas the reality is that the mechanism of acidic cupric chloride etching, regeneration and recovery is complex [Fig 1], and the current monitoring strategies can have difficulty controlling the complex interlocking chemical equilibria. We report that thin-film UV-Vis spectroscopy has the capability to effectively monitor the electrochemical processes and its complex redox changes to the etch bath from beginning to end. We report that the complex equilibria has direct control on the etch rate and its regeneration process. UV-Vis spectroscopy also reveals various underlying mechanism reasons for etch bath behavior and illuminates the roles of H+ and Cl- to the etch bath while also providing a means to monitor the Cl-. By implementing thin film UV-Vis, we are able to probe and monitor the equilibria in real time to maintain a consistent etch rate throughout while also achieving proper regeneration and recovery for repeated use. Additionally, we’ve shown that this technique is sufficient in supplementing oxidation-reduction potential, conductivity, and specific gravity methods. This addition be can utilized to improve current monitoring strategies as it can identify and predict etching behavior that the current standard methodologies may have difficulty predicting. Figure 1

A Effect of Halide on Cobalt Electrodeposition for through-Silicon-Via(TSV) Application

The size of integrated circuit (IC) devices had gradually decreased. Because of limit to reduction, 3D interconnection technology had emerged. As one of the 3D interconnection technologies, Through Silicon Via (TSV) replaced conventional wire bond by making vertical electrical connections. TSVs could increase the device performance because TSV had advantages such as higher interconnection density, shorter length of interconnection, lower power consumption, and lower electrical resistance [1]. TSV was mainly plated with copper with low resistance and low electro-migration. However, copper annealing process, metal interconnect process and bonding process between chips and chips or wafers and wafers were performed at high temperature in BEOL, which causes problems such as thermal extrusion and keep-out zone. Thermal extrusion is enough to make the defect and crack at insulating layer or metal interconnect on TSV. And the keep-out zone could cause some degradation in device performance [3]. Therefore, Cobalt was used to fill TSV as alternative material which can reduce this problem because the CTE of cobalt was lower than that of copper. However, while many studies on copper TSV filling was reported, studies on cobalt TSV filling was insufficient. For the TSV bottom-up filling, TSVs were conventionally filled with some additives such as accelerator and suppressor by using the electrochemical deposition. In addition, halide was used to enhance adsorption of suppressor. Many studies confirmed effect of halide in copper electrodeposition [2, 4]. In this study, high-aspect ratio TSVs was filled with cobalt with suppressor as the single additive using the electrochemical deposition. The filling behavior was affected by suppressor concentration and the effect was saturated. In copper electrodeposition, halide ion is added because adsorption of suppressor is affected by chloride [2, 4]. Therefore, chloride, one of the halide, was added to confirm the effect of halide on cobalt electrodeposition. In cobalt electrodeposition, the role of chloride was different from that of copper electrodeposition. Electrochemical analysis explains the effect of chloride concentration in the cobalt filling. REFERENCES [1] Sanghyun Jin, Geon Wang, and Bongyoung Yoo, “ Through-Silicon-Via (TSV) Filling by Electrodeposition of Cu with Pulse Current at Ultra-Short Duty Cycle”, Journal of The Electrochemical Society, 2013, 160 (12) D3300-D3305 [2] Liu Yang, Aleksandar Radisic, Johan Deconinck, and Philippe M. Vereecken, “ Modeling the Bottom-Up Filling of Through-Silicon vias Through Suppressor Adsorption/Desorption Mechanism”, Journal of The Electrochemical Society, 2013, 160 (12) D3051-D3056 [3] Suk-Kyu Ryu, Kuan-Hsun Lu, Tengfei Jiang, Jang-Hi Im, Senior Member, Rui Huang, and Paul S. Ho, Fellow,“ Effect of Thermal Stresses on Carrier Mobility and Keep-Out Zone Around Through-Silicon Vias for 3-D Integration”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2012, 6, VOL. 12, NO. 2, 255-262 [4] Ning Xiao, Deyu Li, Guofeng Cui, Ning Lia, Qing Li, Gang Wu, “Adsorption behavior of triblock copolymer suppressors during the copper electrodeposition”, Electrochimica Acta, 116 (2014) 284– 291

Self-Annealing Behavior of Electroplated Cu in the Blind-Hole Structure

Blind-hole (BH) metallization via electrolytic Cu fillings has become a critical technology for fabrication of high-density-interconnection (HDI) printed circuit boards in electronic industry because this technology provides excellent thermal and electrical conductivity and efficient utilization of space. The morphology and crystallographic orientation/texture of the Cu fillings governs the electrical, thermal, and mechanical properties of the interconnections, affecting the overall reliability of an electronic device. Although numerous publications concerning the self-annealing behavior (generally termed room-temperature recrystallization) of electroplated Cu, there is still limited information regarding such a time-dependent phenomenon in the BH structure. As the distributions of organic additives and current density in a BH structure is very different from on the flat substrate and is an important factor of Cu self-annealing, it is therefore of fundamental interest and importance to investigate the BH Cu microstructure transition in the self-annealing procedure. In this study, we probed into the crystallographic and resistance transitions of the Cu platings in a BH structure via an ohm meter and a field-emission scanning electron microscope (FE-SEM) in combination with electron backscatter diffraction (EBSD) analysis system. Additionally, the distribution of organic additives in a BH structure was characterized using a time of flight secondary ion mass spectrometer (TOF-SIMS). The knowledge advances our understanding of the evolution of the BH Cu filling physical/chemical properties during self-annealing. Figure 1

An Integrated Radar Tile for Digital Beamforming X-/Ka-Band Synthetic Aperture Radar Instruments

This paper presents the first experimental assessment of a highly integrated dual-band dual-polarized antenna tile designed for synthetic aperture radar (SAR) digital beamforming (DBF) satellite applications. The demonstrator described in this paper is the first comprehensive experimental validation of an RF module providing the X-band and Ka-band (9.6- and 35.75-GHz) operation with custom downconversion stages. All the antennas, transitions, and downconversion chips are integrated in the same antenna tile fabricated using a customized 15-layer high density interconnect process. The designed tile goes to the limits of the proposed technology and for the high trace density and for the size of the vertical transitions. The proposed results represent the state of the art in terms of compactness for a DBF SAR RF module even though the demonstrator was manufactured with a standard low-cost technology. The experimental assessment proves the validity of the proposed manufacturing and integration approaches showing a substantial agreement between the performance of the individual blocks and of the integrated system.