Abstract

Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity (<1 mm separation) compared with several centimeters on a typical PCB. In this paper, we have outlined the benefits of adopting 2.5D TSI technology and also highlighted the current day approaches to implement this technology in Si fabrication facilities, and in assembly/packaging factories. While the systems and devices that power the mobile society benefit from exploiting advantages of 2.5D integration on TSI, there do exist surmountable challenges that need to be addressed for this relatively new technology to be used in high volume production of next generation semiconductor devices. The key areas of focus and challenges include: Technology planning and design-execution that are necessary for harnessing 2.5D TSI for building systems, processing flow for the fabrication of 100 μm thick TSI at acceptable costs, manufacturing flow for assembling multiple ICs on a 100 μm thick TSI in a repeatable, and reliable manner, thermo-mechanical analysis and optimization for addressing warpage issues, and thermal management for addressing heat dissipation. We have outlined design, manufacturing methodologies, and challenges, along with solutions to the challenges associated with taking 2.5D TSI technology to high volume production within the next few years.

Highlights

  • Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs)

  • These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity (

  • We have outlined the benefits of adopting 2.5D TSI technology and highlighted the current day approaches to implement this technology in Si fabrication facilities, and in assembly/packaging factories

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Summary

Thermal characterization of stacked

D. Thermal aware 2.5D design and professionally connected to us. Today’s mobile society leverages on the performance and reliability of mobile devi-. THERMO-MECHANICAL DESIGN AND ces (phones and tablets) and the vast internet infrastructure. A. Manufacturability and functionality of TSI . 40 strongly driven by the large market size and customer base. 1. Design rules for avoiding wafer cracking 41 Continued innovations are needed as the adoption of mobile. 2. Design rules for reducing copper devices rapidly penetrates developed as well as emerging economies of the world. 3. Design for reducing mobility change of such adoption will drive the processing and transfer of large volumes of data in the mobile society

Handling of TSV wafers and chips during
Interconnect bottleneck
More-on-Moore SoC scaling
More-than-Moore system scaling
Application examples
General summary in advancement
Technology planning and design-execution
Processing flow for fabrication of 100 lm thick TSI
Manufacturing flow for assembling multiple ICs on a 100 lm thick TSI
Thermo-mechanical analysis and optimization
Development of next generation manufacturing equipment
TSV module
TSV deep Si etch process
Seed layer and barrier layer deposition
BEOL and RDL scheme
Solder bumping and Cu pillar bumps
Fabrication of Cu pillar micro-bumps
Reliability assessment of Cu pillar bumps
Thin wafer handling
Carrier substrates
Temporary bonding and debonding
Adhesives requirement
TSI package assembly process flow
Assembly Challenges and Warpage Control
Summary
TSV characterization structures
High density wiring characterization
Chip-to-chip link characterization
Micro joint reliability characterization
Decoupling capacitors
10 G SerDes
Passive cooling
TSV thermal enhancement
Effect of TSV interposer on package thermal performance
Thermal characterization of stacked chips
Active air cooling
Liquid cooling
Design
Manufacturability and functionality of TSI
Design rules for avoiding wafer cracking
Design rules for reducing copper protrusion
Handling of TSV wafers and chips during fabrication and assembling
Design for reducing TSV wafer warpage
Design for avoiding die-cracking during chip stacking
Packaging and long-term reliability
CPI and micro solder bump reliability of TSI
Design for enhancing solder joint reliability of packages with Si carrier
EDA CONSIDERATIONS AND READINESS
Technology LEF files
PEX rule decks and TSV extraction
Design import
Floor planning and placement
Parasitic extraction
SI and PI verification
DRC and LVS verification
Application roadmap
Solder technology
Metal-metal bonding
Inability of existing 3D EDA tools to analyze unified 3D netlist
Findings
SUMMARY
Full Text
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