High-density Dynamic Random Access Memory Research Articles

A Better Sense Amplifier Improves the Resilience in Compute-In-Memory and Row Hammer

As machine learning (ML) workloads continue to scale, the demand for higher-density DRAM (Dynamic Random-Access Memory) and SRAM (Static Random-Access Memory) is intensifying, and also driving interest in compute-in-memory (CIM) architectures as a promising approach to enhancing computational efficiency. However, increasing DRAM cell density introduces significant challenges, particularly in the reliable identification of charge sharing between cells and bit lines. This challenge heightens the susceptibility of DRAM to row hammer attacks, where unintended data corruption occurs due to repeated access to adjacent rows. Furthermore, CIM architectures necessitate more precise sensing of bit lines to ensure accurate computation within memory. In light of these challenges, our study proposes an investigation into the potential benefits of utilizing an offset compensation sense amplifier (OCSA). The OCSA is designed to address the accuracy limitations posed by high-density DRAM in CIM applications. By enhancing the precision of bit line sensing, the OCSA may mitigate the vulnerability to row hammer attacks and improve the overall reliability and performance of CIM architectures. This study will explore the effectiveness of the OCSA in maintaining data integrity and computational accuracy within high-density DRAM environments, offering insights into its applicability for future ML workloads.

Low sheet resistance buried metal bit line realized by high-temperature metal CVD process in vertical channel transistor array

With the continuous evolution of dynamic random access memory (DRAM) devices, there is a growing demand for increased storage density per unit area. In this work, we aim to create a high-density array of vertical channel transistors using advanced DRAM process technology. A thickness of SiO2 (X+3 nm) was determined for the protective layer, which shows the best-protecting effect. We employed CVD to grow thin Ti films on the array’s bottom. To reduce the resistance of the buried bit line (BBL), we formed a high-quality metal silicide using a thermal annealing process combined with self-align technology. Nanoprobe measurement results show an average resistance of approximately 60 Ω of the bit line of each cell transistor, where the low series resistance can improve device performance. Our work involved optimizing the protective layers and achieving high-performance BBLs, paving the way for the development of high-density DRAMs.

Retention-Aware DRAM Assembly and Repair for Future FGR Memories

Refresh operations consume substantial energy and bandwidth in high-density dynamic random-access memory (DRAM) memory. The trend of increasing refresh overhead limits the scalability of DRAM memory that refreshes all cells at the same rate, because the refresh rate setting depends on the worst-case weak cell manufactured in unstable process technology. To cope with this issue, fine-grained refresh (FGR) is proposed to eliminate the unnecessary refresh operations caused by minor weak cells. Even JEDEC's DDR4 DRAM specification announces the support of FGR, which is likely to evolve and become a standard in future DRAM. Unfortunately, according to our key observation, the effectiveness of FGR is greatly confined by the procedure of refresh-oblivious device integration because all memory devices within a module have to be controlled and refreshed in a lockstep way after the step of assembly. In this paper, we are the first to propose a holistic FGR-oriented DRAM optimization framework, retention-aware DRAM assembly and repair (RADAR), to enhance the effectiveness of FGR in DRAM modules. RADAR includes two novel techniques applicable at the stage of DRAM assembly. The first one is retention-aware device clustering that integrates the “compatible” devices to achieve low refresh rate through a preassembly testing and retention-aware matching method. The second technique, Microfix, exploits the hierarchical DRAM array structure and its redundancy to fix critical weak DRAM rows through fine-grained row and subarray remapping. With this optimization architecture, RADAR, the refresh overhead of DRAM dual in-line memory modules can be dramatically reduced as implied in the experiments.

A Vertically Integrated Capacitorless DRAM Cell

A capacitorless cell with only 2 terminals is presented for high-density dynamic random access memory applications. Experiments and calibrated simulations were conducted, which prove that this memory cell has high operation speed (ns level), large read current margin (a read current ratio of 104), low process variation, good thermal reliability and available retention time (190ms). Furthermore, the memory cell is compatible with CMOS technology and free of cyclic endurance problem induced by hot-carrier injection due to the gateless structure.

ChemInform Abstract: A Stacked Capacitor Cell with a Fully Self-Aligned Contact Process for High-Density Dynamic Random Access Memories (DRAM).

ChemInform is a weekly Abstracting Service, delivering concise information at a glance that was extracted from about 100 leading journals. To access a ChemInform Abstract of an article which was published elsewhere, please select a “Full Text” option. The original article is trackable via the “References” option.

High Density Capacitorless Dynamic Random Access Memory Cell with Quasi Silicon-on-Insulator Structure Based on Bulk Substrate

A novel quasi silicon-on-insulator (QSOI) capacitorless dynamic random access memory (DRAM) Cell with bulk substrate is proposed and investigated for the first time. The QSOI DRAM cell is based on the promising highly scalable QSOI device structure. The deep L-shape layer of proposed QSOI cell can provide isolation between adjacent cells along bit line, without increasing the cell area as the one transistor (1T) bulk capacitorless DRAM cell. The electrical performance of this structure is also studied and compared with 1T-bulk cell. Longer retention time and larger sensing margin can be achieved in the proposed QSOI cell, due to the suppressed leakage current. The results indicate that QSOI cell has great potentials for high density DRAM applications.

Using Embedded Dynamic Random Access Memory to Reduce Energy Consumption of Magnetic Recording Read Channel

Although the performance of a magnetic recording read channel can be improved by employing advanced iterative signal detection and coding techniques, the method nevertheless tends to incur significant silicon area and energy consumption overhead. Motivated by recent significant improvement of high-density embedded dynamic random access memory (eDRAM) towards high manufacturability at low cost, we explored the potential of integrating eDRAM in read channel integrated circuits (IC) to minimize the silicon area and energy consumption cost incurred by iterative signal detection and coding. As a result of the memory-intensive nature of iterative signal detection and coding algorithms, the silicon cost can be reduced in a straightforward manner by directly replacing conventional SRAM with eDRAM. However, reducing the energy consumption may not be trivial. In this paper, we present two techniques that trade eDRAM storage capacity to reduce the energy consumption of iterative signal detection and coding datapath. We have demonstrated dDRAM's energy saving potential by designing a representative iterative read channel at the 65 nm technology node. Simulation shows that we can eliminate over 99.99% of post-processing computation for dominant error events detection, and achieve up to a 67% reduction of decoding energy consumption.

X-Ray Radiation Effect in DRAM Retention Time

For quality verification, an X-ray inspection process is commonly being used for evaluating obscured and defective solder joints in surface-mount technologies, such as ball grid arrays and flip chips. Integrated circuits subjected to any form of radiation, i.e., ionizing or nonionizing, may incur some amount of damage depending on the absorbed dose. Though most X-ray inspections for high-quality imaging require ionizing dose amounts that are considered inconsequential for device failure or non-functionality, the degree of latent damage must be carefully considered. This paper discusses X-ray-induced vulnerabilities of high-density dynamic random access memory exposed to low ionizing radiation levels typical in X-ray inspection systems. We look at critical parameters and their sensitivity in relation to varying dose amounts of X-ray irradiation. In consideration of different methodologies of reducing radiation dose amounts and limiting device exposure, we propose a procedure for attenuating potentially harmful X-ray radiation levels while preserving quality images.

Effect of Fluorine on Characteristics of Shallow Trench Isolation Prepared Using High-Density Plasma Chemical Vapor Deposition Including NF3 Chemistry

We investigated whether the fluorine of the field oxide affected gate oxide reliability and some isolation characteristics of metal–oxide semiconductor (MOS) transistors for high-density dynamic random-access memory (DRAM). Fluorine was incorporated during high density plasma (HDP) chemical vapor deposition (CVD) using NF3 chemistry for better shallow trench isolation (STI) gap-filling ability. Considerable fluorine included in the field oxide during deposition diffused from the field oxide to the silicon surface of a shallow trench during the subsequent thermal processes. This fluorine of the field oxide did not degrade the gate oxide reliability such as SILC and charge-to-breakdown characteristics. Moreover, it could improve various transistor characteristics such as the junction leakage, isolation punch-through current and data retention time of a DRAM device. It was inferred that some improvement of the MOS transistor was obtained by the interaction of Si interface traps near the trench wall with fluorine and the reduction of the density of Si interface traps.

Pulsed laser deposition of PZT/Pt composite thin films with high dielectric constants

PbZr0.53Ti0.47O3 (PZT) thin films containing nanoparticles of Pt (3–10 nm) were produced using pulsed laser deposition (PLD). The Pt content can be tuned by varying the energy density of the laser beam. Phase and microstructure analysis of the thin films was performed using XRD, SEM, TEM and AFM. The electrical properties were investigated by C–V and I–V measurements. The effective dielectric constant of the composite films increased substantially through the Pt dispersion. These films are promising candidates, for instance, for high-density dynamic random access memory (DRAM) devices.

Eliminating the Threshold-Voltage Offset of p-Channel Metal-Oxide-Semiconductor Field Effect Transistors in High-Density Dynamic Random Access Memory

The threshold voltage offsets of paired p+-gate p-channel metal-oxide-semiconductor field effect transistors in high-density dynamic random access memory is investigated. The threshold voltage offset is shown to be mainly due to segregation of phosphorus at the edges of the shallow trench isolation when the gate oxide is formed. A 20-mV threshold-voltage offset was experimentally eliminated through control of the phosphorus concentration and the layout of the cross-couplings of sense amplifiers. It is expected that reduction in the threshold voltage offset will improve the retention times of gigabit-scale dynamic random access memory.

Ruthenium Bottom Electrode Prepared by Electroplating for a High Density DRAM Capacitor

The possibility of Ru electroplating for application as the bottom electrode in high density dynamic random access memory (DRAM) capacitors was investigated. Prior to Ru electroplating on a TiN substrate, HF cleaning and Pd activation were performed. Removal of Ti oxide from the TiN substrate by HF treatment enabled Pd activation, which enhanced the nucleation of Ru on TiN substrate. Optimized pretreatments led to a continuous Ru film deposition. The surface roughness was measured to be 4.4 nm at 45 nm Ru film on the bare substrate. Moreover Ru electroplating method was also applied to a capacitor node-type TiN wafer. The deposition rate of Ru on the patterned wafer was the same as that on a bare wafer. The film showed 93% step coverage and good adhesion, comparable to CVD Ru films. © 2004 The Electrochemical Society. All rights reserved.

Impact of Localized Channel and Field Implantation on Data Retention Time for Gigabit Density DRAM Technology

As the density of dynamic random access memories (DRAMs) enters into giga-bit regime with deep sub-quarter-micrometer feature size, the control of junction leakage current at storage node becomes much more important because of increased channel doping concentration. In this paper, we analyzed the junction leakage current of cell transistor and suggested effective cell structure to improve the data retention time for mass-produced 512 Mb DRAM with 0.12 μm. This cell structure, which is based on localized channel and field implantation, reduces the junction leakage current by relaxing junction doping profile and implantation damages at source and drain regions. The relaxed junction profile can reduce the electric field strength of a junction and thus improve data retention time in DRAMs. In addition, subthreshold characteristics of a cell transistor are improved dramatically with this scheme by increasing threshold voltage of corner transistor that is generally lowered by boron segregation and field crowding at the shallow trench isolation boundary in the conventional cell transistor. The proposed approach reduced the cumulative fail-bit probability by about 80% at the data retention time of 128 ms and possibly, can be applied to future high density DRAMs with feature size down to 0.1 μm range. © 2003 The Electrochemical Society. All rights reserved.

Optimization of process conditions for the formation of hemispherical-grained (HSG) silicon in high-density DRAM capacitor

We have compared the capacitances of a conventional stacked capacitor and hemispherical-grained silicon (HSG-Si), in which the seeding method was applied to storage electrode of 64 Mbit dynamic random access memory (DRAM) through Si 2H 6-molecule irradiation and annealing for HSG-Si formation. Also, we considered the variation of the HSG-Si thickness due to the phosphorus concentration of storage poly-silicon in process condition and the effect of its thickness on the cell capacitance and failure occurrence, etc. We investigated the effect of the deposition temperature of amorphous poly-silicon on the HSG-Si formation. As a result, the optimum process conditions of the phosphorus concentration, the deposition temperature of storage poly-silicon and the HSG thickness in HSG formation are 3.5–4.5×10 19 atoms/cm 3, 530°C and 450 Å, respectively. It is found that the limit thickness of dielectric film of 64 Mbit DRAM capacitor according to the optimized process condition is 65 Å.

High Performance Cell Transistor for Long Data Retention Time in Giga-bit Density Dynamic Random Access Memory and Beyond

High performance cell transistor was proposed for long data retention time in mass-produced 512 Mb dynamic random access memory (DRAM) with 0.12 µm design rule. Since process-induced trap density and electric field at the storage node junction should be reduced to improve data retention time, we designed a cell transistor using localized channel and field implantation (LOCFI) scheme. Using LOCFI scheme, the data retention time was nearly doubled by virtue of reduced cell leakage current resulting from the suppressed ion implantation damage and the reduced electric field at the storage node simultaneously. In addition, it was found that the hydrogen annealing after trench etching, the double gate spacer consisting of CVD oxide and Si3N4 layer, and the chemical downstream Si treatment after storage node contact etching significantly improved the data retention time. These proposed approaches for longer data retention time can be applied to future high density DRAMs with feature size down to 0.1 µm range.

High performance of novel oxygen diffusion barrier materials for future high-density dynamic random access memory devices

A new design concept for diffusion barriers in highdensity memory capacitors was suggested, and both the RuTiN and the RuTiO films, as sacrificial oxygen diffusion barriers, were proposed. Contact resistance, the most important electrical parameter for the diffusion barrier in the bottom electrode structure of capacitors, exhibited as low as 5 kΩ even after annealing up to 750 °C. The capacitance behavior of the simple stack-type structure adopted TiNbarrier layer initially degraded after annealing at 500 °C, and thereafter, completely failed. In the case of the RuTiN barrier layer, however, the capacitance was shown to be more than 28 fF/cell up to 600 °C. Correspondingly, the RuTiN film, as a sacrificial oxygen diffusion barrier for high-density capacitors, exhibited much higher diffusion barrier performance than the TiN barrier layer.

Feasibility of a neutron detector-dosemeter based on single-event upsets in dynamic random-access memories.

The feasibility was investigated of a solid-state neutron detector/dosemeter based on single-event upset (SEU) effects in dynamic random-access memories (DRAMs), commonly used in computer memories. Such a device, which uses a neutron converter material to produce a charged particle capable of causing an upset, would be light-weight, low-power, and could be read simply by polling the memory for bit flips. It would have significant advantages over standard solid-state neutron dosemeters which require off-line processing for track etching and analysis. Previous efforts at developing an SEU neutron detector/dosemeter have suffered from poor response, which can be greatly enhanced by selecting a modern high-density DRAM chip for SEU sensitivity and by using a thin 10B film as a converter. Past attempts to use 10B were not successful because the average alpha particle energy was insufficient to penetrate to the sensitive region of the memory. This can be overcome by removing the surface passivation layer before depositing the 10B film or by implanting 10B directly into the chip. Previous experimental data show a 10(3) increase in neutron sensitivity by chips containing borosilicate glass, which could be used in an SEU detector. The results are presented of simulations showing that the absolute efficiency of an SEU neutron dosemeter can be increased by at least a factor of 1000 over earlier designs.

The fabrication and characteristics of (Ba 0.5Sr 0.5)TiO 3 thin films prepared by pulsed laser deposition

The fabrication and characteristics of (Ba 0.5Sr 0.5)TiO 3 (BST) thin films prepared by sputtering (Ba 0.5Sr 0.5)TiO 3 targets were investigated. The laser-deposited BST films were grown on Si (1 0 0) substrates at 700°C under an oxygen pressure of 0.1 Pa. The capacitance–voltage behavior of metal–insulator–metal structures and their leakage current characteristics were studied. The results showed that the dielectric constant of 40 nm thick BST films was 150, and the dissipation factor was 0.035 at 1 MHz. The leakage current density was 2×10 −9 A/cm 2 at 2 V. The high dielectric constant, low dielectric loss, and low leakage current show the potential of (Ba 0.5Sr 0.5)TiO 3 thin films for integrated capacitors and high-density dynamic random access memories.

Low-Damage Gate Etching with High Degree of Anisotropy in High-Density DRAM Cell

We have investigated low-damage gate etching with a high degree of anisotropy in a high-density dynamic random access memory (DRAM) cell. In this paper, we propose the bias combination mode as an effective gate etch scheme, in which time modulation (TM) bias is applied to the high-Vpp (peak-to-peak value of bias voltage) main etching and continuous wave(CW) bias is applied to low-Vpp overetching. In addition, we report, for the first time, that the gate etching method employing the bias combination mode enables us to improve the degree of anisotropy significantly, while still keeping a good tail component of the retention time for 0.18 µm DRAM and beyond.

Interfacial charge trapping inextrinsic Y2O3/SiO2 bilayer gatedielectric based MIS devices on Si(100)

Metal-insulator-semiconductor (MIS) structuresbased on an extrinsic Y2O3 dielectric film on Si showhigh leakage currents due to roughness-related highly localizedfields. Oxygen annealing increases the dielectric constant andstrength and reduces leakage currents by transformingY2O3 (film)/Si(100) into a bilayerY2O3 (film)/SiO2/Si(100) dielectricstructure. Evolution of interfacial SiO2 causesgeneration of mid-gap interface states at Ev + 0.23 eV and Ev + 0.43 eV, which act as electron trapsand are responsible for hysteresis effects incapacitance-voltage (C-V) andcurrent-voltage (I-V) behaviour in theaccumulation-inversion modes. The electron trappingreduces the cathodic field and causes lowering of the currentand the shift in current to higher fields after successiveramps. The charge trapping effects cause varied and unstableC-V and I-V behaviour of MIS structures based on a Y2O3/SiO2 bilayer gate dielectric. Its origin hasbeen attributed to microstructure and defect state modificationat the Y2O3 film-Si interface. This limitsits application in high-density dynamic random access memory andultra-large-scale integration devices.