High Performance Cell Transistor for Long Data Retention Time in Giga-bit Density Dynamic Random Access Memory and Beyond

Abstract

High performance cell transistor was proposed for long data retention time in mass-produced 512 Mb dynamic random access memory (DRAM) with 0.12 µm design rule. Since process-induced trap density and electric field at the storage node junction should be reduced to improve data retention time, we designed a cell transistor using localized channel and field implantation (LOCFI) scheme. Using LOCFI scheme, the data retention time was nearly doubled by virtue of reduced cell leakage current resulting from the suppressed ion implantation damage and the reduced electric field at the storage node simultaneously. In addition, it was found that the hydrogen annealing after trench etching, the double gate spacer consisting of CVD oxide and Si3N4 layer, and the chemical downstream Si treatment after storage node contact etching significantly improved the data retention time. These proposed approaches for longer data retention time can be applied to future high density DRAMs with feature size down to 0.1 µm range.